XRT79L71IB datasheet(35/109 Pages) EXAR

35 / 109 page

XRT79L71

REV. 1.0.0

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

TxPMod

Transmit PPP Data Bus - Modulo Indicator:

This input pin is used to specify the number of valid packet octets are being

placed on the TxPData[15:0] input pins.

The Link Layer Processor is expected to set this input pin "Low" when both bytes

on the TxPData[15:0] data bus contains valid packet data. Conversely, the Link

Layer Processor is expected to set this input pin "High" when only the upper

octet contains valid packet data.

NOTES:

This input pin is only active if the XRT79L71 has been configured to

operate in the PPP Mode and if the Transmit POS-PHY Data Bus has

been configured to be 16-bits wide. In all other case, the user should tie

this input pin to GND.

The Link Layer Processor is expected to set this input pin to the

appropriate state, as each 16-bit word is being written into the

TxPData[15:0] data bus.

TxUData_0/

TxPData_0

TxUData_1/

TxPData_1

TxUData_2/

TxPData_2

TxUData_3/

TxPData_3

TxUData_4/

TxPData_4

TxUData_5/

TxPData_5

TxUData_6/

TxPData_6

TxUData_7/

TxPData_7

TxUData_8/

TxPData_8

TxUData_9/

TxPData_9

TxUData_10/

TxPData_10

TxUData_11/

TxPData_11

TxUData_12/

TxPData_12

TxUData_13/

TxPData_13

TxUData_14/

TxPData_14

TxUData_15/

TxPData_15

Transmit UTOPIA Data Bus Inputs/Transmit POS-PHY Data Bus Inputs:

The function of these input pins depends upon whether the XRT79L71 is operat-

ing in the ATM UNI Mode or in the PPP Mode as described below.

ATM UNI Operation - TxUData[15:0] ] - Transmit UTOPIA Interface Data Bus

Input pins:

These input pins comprise the Transmit UTOPIA Data Bus input pins. Whenever

the ATM Layer Processor wishes to transmit ATM cell data through the

XRT79L71 ATM UNI, it must place this data on these pins. The data, on the

Transmit UTOPIA Data Bus is latched into the Transmit UTOPIA Interface block

upon the rising edge of TxUClk.

NOTES:

These input pins are only active (e.g., data will be sampled and latched

into the Transmit UTOPIA Interface block) if the TxUEN input pin is

asserted (e.g., pulled "Low").

If the user configures the width of the Transmit UTOPIA Data Bus to be

8-bits, then only the pins TxUData[15:8] are active. In this case, the

user must tie the TxUData[7:0] input pins to GND.

PPP Operation - TxPDATA[15:0] - Transmit POS-PHY Data Bus Input pins:

These input pins comprise the Transmit POS-PHY Data Bus input pins. When a

Link Layer Processor transmits PPP packet data through the XRT79L71, it must

place this data on these pins. The data, on the Transmit POS-PHY Data Bus is

latched into the Transmit POS-PHY Interface block upon the rising edge of TxP-

Clk.

NOTES:

These input pins are only active (e.g., data will be sampled and latched

into the Transmit POS-PHY Interface block) if the TxPENB input pin is

asserted (e.g., pulled "Low").

If the user configures the width of the Transmit POS-PHY Data Bus to

be 8-bits, then only the pins TxPData[15:8] are active. In this case, the

user must tie the TxPData[7:0] input pins to GND.

The user should tie all of these pins to GND to operate the XRT79L71

in either the Clear-Channel Framer or in the High-Speed HDLC

Controller Modes.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 35 Page - Exar Corporation

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