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XRT79L71IB Datasheet(PDF) 63 Page - Exar Corporation |
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XRT79L71IB Datasheet(HTML) 63 Page - Exar Corporation |
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63 / 109 page  XRT79L71 60 REV. 1.0.0 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE NOTE: The Receive FEAC Controller Block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity Framing format. The Receive LAPD Controller Block The purpose of the Receive LAPD Controller block is to permit the user to receive LAPD/PMDL (Path Maintenance Data Link) Messages from the remote terminal equipment. The Receive LAPD Controller block comes with a Receive LAPD Controller and 90 bytes of on-chip RAM (for storage of inbound PMDL Messages) after reception. The Receive Payload Data Output Interface Block The purpose of the Receive Payload Data Output Interface block is to output payload data (within the incoming DS3 or E3 data-stream) via either a Serial or Nibble-Parallel interface, and to route this data to the off-chip System-Side Terminal Equipment. The Receive Overhead Data Output Interface Block The purpose of the Receive Overhead Data Output Interface block is to permit the user to extract out the overhead bits (within the incoming DS3/E3 data-stream) and to route this data to some off-chip System-Side Terminal Equipment circuitry. A MORE DETAILED FUNCTIONAL/ARCHITECTURAL DESCRIPTION FOR CLEAR-CHANNEL FRAMER MODE BRIEF FUNCTIONAL ARCHITECTURE DESCRIPTION OF THE XRT79L71 - HIGH-SPEED HDLC CONTROLLER OVER DS3/E3 MODE If the XRT79L71 has been configured to operate in the High-Speed HDLC Controller over DS3/E3 Mode, then it will have the Functional Architecture as is presented below in Figure 3. Figure 3 indicates that the XRT79L71 consists of the following functional blocks. FIGURE 3. THE FUNCTIONAL BLOCK DIAGRAM OF THE XRT79L71 WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE HIGH-SPEED HDLC CONTROLLER OVER DS3/E3 MODE Transmit HDLC Controller Block Transmit DS3/E3 Framer Block Transmit DS3/E3 LIU Block Transmit DS3/E3 LIU Block Receive DS3/E3 LIU Block Receive DS3/E3 LIU Block Receive DS3/E3 Framer Block Receive HDLC Controller Block Microprocessor Interface MOTO D[7:0] A[8:0] IntB* CSB* RdB_DS WrB_RW Rdy_Dtck Reset* ALE_AS TTIP TRING Tx LAPD Buffer/ Controller Rx LAPD Buffer/ Controller TxHDLCDat[7:0] TxHDLCClk SEND_MSG SEND_FCS RxHDLCDat[7:0] RxHDLCClk VAL_FCS IDLE_FLAG DS3/E3 Jitter Attenuator Block DS3/E3 Jitter Attenuator Block DS3/E3 Jitter Attenuator Block DS3/E3 Jitter Attenuator Block RRING RTIP Only one JA exists. Can be configured in Tx or Rx Path |
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