XRT79L71IB datasheet(44/109 Pages) EXAR

44 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

RxPOH_Clk/

RxClk/

RxNibClk

Receive PLCP Path Overhead Serial Port Clock output/Receive Nibble-

Parallel Output port clock/Receive Serial Clock output:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the ATM/PLCP Mode or the Clear-Channel Framer

Mode.

ATM/PLCP Mode - RxPOH_Clk:

This output clock pin along with RxPOH, RxPOHFrame and RxPOHIns pins

comprise the Receive PLCP Frame POH Byte serial output port. All POH (Path

Overhead) data that is output via the RxPOH output pin is updated on the rising

edge of this clock signal.

NOTE: This output signal is inactive if the XRT79L71 has been configured to

operate in the Direct-Mapped ATM Mode.

Clear-Channel Framer Mode - RxClk:

This output pin is active whenever the XRT79L71 has been configured to oper-

ate in either the Serial or Nibble Parallel Mode, as is described below.Clear-

Channel Framer/Serial Mode - RxClkIn this serial mode, this output is a

44.736MHz clock output signal (for DS3 applications) or 34.368MHz clock out-

put signal (for E3 applications). The Receive Payload Data Output Interface will

update the data via the RxSer output pin, upon the rising edge of this clock sig-

nal.

The user is advised to design (or configure) the System-Side terminal equip-

ment to sample the RxSer data, upon the falling edge of this clock signal.

Clear-Channel Framer/Nibble-Parallel Mode - RxNibClk:

In the Nibble-Parallel Mode, the XRT79L71 will derive this clock signal from the

RxLineClk signal. The XRT79L71 will pulse this clock signal 1176 times for

each inbound DS3 frame or 1074 times for each inbound E3/ITU-T G.832 frame

or 384 times for each inbound E3/ITU-T G.751 frame. The Receive Payload

Data Output Interface block will update the data on the RxNib[3:0] output upon

the falling edge of this clock signal.

The user is advised to design (or configure) the System-Side terminal equip-

ment to sample the data on the RxNib[3:0] output pins, upon the rising edge of

this clock signal.

RxPOHFrame

Receive PLCP Frame POH Serial Output Port - Frame Indicator:

This output pin along with the RxPOH RxPOHClk and RxPOHIns pins comprise

the Receive PLCP Frame POH Byte serial output port. This output pin provides

framing information to external circuitry receiving and processing this POH

(Path Overhead) data, by pulsing "High" whenever the first bit of the Z6 byte is

being output via the RxPOH output pin. This pin is "Low" at all other times dur-

ing this PLCP POH Framing cycle.

NOTE: This output pin is only active if the XRT79L71 has been configured to

operate in the ATM/PLCP Modes.

PIN #NAME

TYPE

DESCRIPTION

XRT79L71IB Datasheet(PDF) 44 Page - Exar Corporation

XRT79L71IB Datasheet(HTML) 44 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL