XRT79L71IB datasheet(36/109 Pages) EXAR

36 / 109 page

XRT79L71

1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0

PIN #

NAME

TYPE

DESCRIPTION

RECEIVE SYSTEM SIDE INTERFACE PINS

RxAIS/

RxNib_2/

RxHDLCDat_2

Receive AIS Pattern Indicator/Receive Nibble Output Interface - Bit 2/

Receive HDLC Controller Data Bus - Bit 2 output pin:

The function of this output pin depends upon whether the XRT79L71 has been

configured to operate in the Clear-Channel Framer/Nibble-Parallel Interface

Mode, the High-Speed HDLC Controller Mode, or in the other modes.

Other Modes - RxAIS - AIS Defect Indicator Output Pin:

This output pin is driven "High" whenever the Receive DS3/E3 Framer block

has detected and is currently declaring the AIS (Alarm Indicator Signal) defect.

Clear-Channel Framer/Nibble-Parallel Interface Mode - RxNib_2:

If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this

output pin will function as the bit 2 output from the Receive Nibble-Parallel out-

put interface. The Receive Payload Data Output Interface block will output this

signal (along with RxNib_0, RxNib_1, and RxNib_3) upon the rising edge of the

RxClk output signal.

High-Speed HDLC Controller Mode - Receive High Speed HDLC Controller

Output Interface Block - Data Bus Output Pin #2 - RxHDLCDat_2:

This output pin along with RxHDLCDat_[7:3] and RxHDLCDat_[1:0] functions

as the Receive High-Speed HDLC Controller Output Interface byte wide output

data bus. The Receive High-Speed HDLC Controller outputs the contents of all

HDLC frames and flag sequence octets via this output data bus, upon the rising

edge of the RxHDLCClk output signal. Hence, the user's System-Side terminal

equipment should be designed/configured to sample this data upon the falling

edge of the RxHDLCClk output clock signal.

XRT79L71IB Datasheet(PDF) 36 Page - Exar Corporation