XRT86VL32IB datasheet(28/65 Pages) EXAR

28 / 65 page

XRT86VL32

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

REV. V1.2.0

RxCHCLK0

RxCHCLK2

H17

Receive Channel Clock Output (RxCHCLKn):

The exact function of this pin depends on whether or not the

receive framer enables the receive fractional/signaling interface

to output fractional data, as described below.

If receive fractional/signaling interface is disabled:

This pin indicates the boundary of each time slot of an inbound

DS1/E1 frame. In T1 mode, each of these output pins is a

192kHz clock which pulses "High" during the LSB of each 24

time slots. In E1 mode, each of these output pins is a 256kHz

clock which pulses "High" during the LSB of each 32 time slots.

System Equipment can use this clock signal to sample the

RxCHN0 through RxCHN4 time slot identifier pins to determine

which time slot is being output.

If receive fractional/signaling interface is enabled:

RxCHCLKn is the fractional interface clock which either outputs

a clock signal for the time slot that has been configured to out-

put fractional data, or outputs an enable signal for the fractional

time slot so that fractional data can be clocked out of the device

using the RxSERCLK pin.

NOTE:

Receive fractional interface can be enabled by

programming to bit 4 - RxFr1544/RxFr2048 bit from

RECEIVE SYSTEM SIDE INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

XRT86VL32IB Datasheet(PDF) 28 Page - Exar Corporation