XRT86VL32IB datasheet(40/65 Pages) EXAR

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XRT86VL32

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

REV. V1.2.0

V12

Microprocessor Interface—Write Strobe Input

The exact behavior of this pin depends upon the type of Micro-

processor/Microcontroller the XRT86VL32 has been configured

to operate in, as defined by the PTYPE[2:0] pins.

Intel-Asynchronous Mode - WR* - Write Strobe Input:

This input pin functions as the WR* (Active Low WRITE Strobe)

input signal from the Microprocessor. Once this active-low sig-

nal is asserted, then the input buffers (associated with the Bi-

Directional Data Bus pin, D[7:0]) will be enabled.

The Microprocessor Interface will latch the contents on the Bi-

Directional Data Bus (into the “target” register or address loca-

tion, within the XRT86VL32) upon the rising edge of this input

pin.

Motorola-Asynchronous Mode - R/W* - Read/Write Opera-

tion Identification Input Pin:

This pin is functionally equivalent to the “R/W*” input pin. In the

Motorola Mode, a “READ” operation occurs if this pin is held at

a logic “1”, coincident to a falling edge of the RD/DS* (Data

Strobe) input pin. Similarly a WRITE operation occurs if this pin

is at a logic “0”, coincident to a falling edge of the RD/DS* (Data

Strobe) input pin.

Power PC 403 Mode - R/W* - Read/Write Operation Identifi-

cation Input:

This input pin will function as the “Read/Write Operation Identi-

fication Input” pin.

Anytime the Microprocessor Interface samples this input signal

at a logic low (while also sampling the CS* input pin “low”) upon

the rising edge of PCLK, then the Microprocessor Interface will

(upon the very same rising edge of PCLK) latch the contents of

the Address Bus (A[14:0]) into the Microprocessor Interface cir-

cuitry, in preparation for this forthcoming READ operation. At

some point (later in this READ operation) the Microprocessor

will also assert the DBEN*/OE* input pin, and the Microproces-

sor Interface will then place the contents of the “target” register

(or address location within the XRT86VL32 device) upon the

Bi-Directional Data Bus pins (D[7:0]), where it can be read by

the Microprocessor.

Anytime the Microprocessor Interface samples this input signal

at a logic high (while also sampling the CS* input pin a logic

“low”) upon the rising edge of PCLK, then the Microprocessor

Interface will (upon the very same rising edge of PCLK) latch

the contents of the Address Bus (A[14:0]) into the Microproces-

sor Interface circuitry, in preparation for the forthcoming WRITE

operation. At some point (later in this WRITE operation) the

Microprocessor will also assert the RD*/DS*/WE* input pin, and

the Microprocessor Interface will then latch the contents of the

Bi-Directional Data Bus (D[7:0]) into the contents of the “target”

MICROPROCESSOR INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

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