XRT86VL32IB datasheet(33/65 Pages) EXAR

33 / 65 page

XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

JTAG INTERFACE

The XRT86VL32 device’s JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry

specification for additional information on boundary scan operations.

SIGNAL NAME

BALL #

TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

TCK

Test clock: Boundary Scan Test clock input:

The TCLK signal is the clock for the TAP controller, and it

generates the boundary scan data register clocking. The data

on TMS and TDI is loaded on the positive edge of TCK. Data

is observed at TDO on the falling edge of TCK.

TMS

Test Mode Select: Boundary Scan Test Mode Select input.

The TMS signal controls the transitions of the TAP controller

in conjunction with the rising edge of the test clock (TCK).

NOTE:

For normal operation this pin MUST be pulled "High".

TDI

Test Data In: Boundary Scan Test data input

The TDI signal is the serial test data input.

NOTE:

This pin is internally pulled ’high’.

TDO

Test Data Out: Boundary Scan Test data output

The TDO signal is the serial test data output.

TRST

Test Reset Input:

The TRST signal (Active Low) asynchronously resets the TAP

controller to the Test-Logic-Reset state.

NOTE:

This pin is internally pulled ’high’

TESTMODE

B11

Factory Test Mode Pin

NOTE:

This pin is internally pulled ’low’, and should be pulled

’low’ for normal operation.

aTESTMODE

Factory Test Mode Pin

NOTE:

This pin is internally pulled ’low’, and should be pulled

’low’ for normal operation.

ATP_Ring

ATP_Ring Test Pin

This analog test pin is used for testing the continuity between

the TTIP/TRING, RTIP/RRING of each channel and the on-

board transformer.

ATP_Tip

ATP_Tip Test Pin

This analog test pin is used for testing the continuity between

the TTIP/TRING, RTIP/RRING of each channel and the on-

board transformer.

XRT86VL32IB Datasheet(PDF) 33 Page - Exar Corporation

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