XRT86VL32IB datasheet(41/65 Pages) EXAR

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XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

ACK0

ACK1

DMA Cycle Acknowledge Input—DMA Controller 0 (Write):

The external DMA Controller will assert this input pin “Low”

when the following two conditions are met:

1. After the DMA Controller, within the Framer has asserted

(toggled “Low”), the Req_0 output signal.

2. When the external DMA Controller is ready to transfer

data from external memory to the selected Transmit

HDLC buffer.

At this point, the DMA transfer between the external memory

and the selected Transmit HDLC buffer may begin.

After completion of the DMA cycle, the external DMA Controller

will negate this input pin after the DMA Controller within the

Framer has negated the Req_0 output pin. The external DMA

Controller must do this in order to acknowledge the end of the

DMA cycle.

DMA Cycle Acknowledge Input—DMA Controller 1 (Read):

The external DMA Controller asserts this input pin “Low” when

the following two conditions are met:

1. After the DMA Controller, within the Framer has asserted

(toggled "Low"), the Req_1 output signal.

2. When the external DMA Controller is ready to transfer

data from the selected Receive HDLC buffer to external

memory.

At this point, the DMA transfer between the selected Receive

HDLC buffer and the external memory may begin.

After completion of the DMA cycle, the external DMA Controller

will negate this input pin after the DMA Controller within the

Framer has negated the Req_1 output pin. The external DMA

Controller will do this in order to acknowledge the end of the

DMA cycle.

NOTE:

This pin is internally pulled “High” with a 50k

Ω resistor.

BLAST

U10

Last Cycle of Burst Indicator Input:

If the Microprocessor Interface is operating in the Intel-I960

Mode, then this input pin is used to indicate (to the Micropro-

cessor Interface block) that the current data transfer is the last

data transfer within the current burst operation.

The Microprocessor should assert this input pin (by toggling it

“Low”) in order to denote that the current READ or WRITE

operation (within a BURST operation) is the last operation of

this BURST operation.

NOTES:

If the user has configured the Microprocessor

Interface to operate in the Intel-Asynchronous, the

Motorola-Asynchronous or the Power PC 403 Mode,

then he/she should tie this input pin to GND.

This pin is internally pulled “High” with a 50k

resistor.

MICROPROCESSOR INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

XRT86VL32IB Datasheet(PDF) 41 Page - Exar Corporation

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