XRT86VL32IB datasheet(35/65 Pages) EXAR

35 / 65 page

XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

REQ1

DMA Cycle Request Output—DMA Controller 1 (Read):

These output pins are used to indicate that DMA transfers

(Read) are requested by the T1/E1 Framer.

On the receive side (i.e., To transmit data from HDLC buffers

within the XRT86VL32 to external DMA Controller), DMA trans-

fers are only requested when the receive buffer contains a

complete message or cell.

The DMA Read cycle starts by T1/E1 Framer asserting the

DMA Request (REQ1) ‘low’, then the external DMA controller

should drive the DMA Acknowledge (ACK1) ‘low’ to indicate

that it is ready to receive the data. The T1/E1 Framer should

place new data on the Microprocessor data bus each time the

Read Signal is Strobed low if the RD is configured as a Read

Strobe. If RD is configured as a direction signal, then the T1/E1

Framer would place new data on the Microprocessor data bus

each time the Write Signal (WR) is Strobed low.

The Framer asserts this output pin (toggles it "Low") when one

of the Receive HDLC buffer contains a complete HDLC mes-

sage that needs to be read by the µC/µP.

The Framer negates this output pin (toggles it “High”) when the

Receive HDLC buffers are depleted.

INT

Interrupt Request Output:

This active-low output signal will be asserted when the

XRT86VL32 device is requesting interrupt service from the

Microprocessor. This output pin should typically be connected

to the “Interrupt Request” input of the Microprocessor.

The Framer will assert this active "Low" output (toggles it "Low"),

to the local µP, anytime it requires interrupt service.

PCLK

Microprocessor Clock Input:

This clock input signal is only used if the Microprocessor Inter-

face has been configured to operate in the Synchronous

Modes (e.g., Power PC 403 Mode). If the Microprocessor Inter-

face is configured to operate in this mode, then it will use this

clock signal to do the following.

1. To sample the CS*, WR*/R/W*, A[14:0], D[7:0], RD*/DS*

and DBEN input pins, and

2. To update the state of the D[7:0] and the RDY/DTACK

output signals.

NOTES:

The Microprocessor Interface can work with PCLK

frequencies ranging up to 33MHz.

This pin is inactive if the user has configured the

Microprocessor Interface to operate in either the Intel-

Asynchronous or the Motorola-Asynchronous Modes.

In this case, the user should tie this pin to GND.

When DMA interface is enabled, the PCLK input pin is also

used by the T1/E1 Framer to latch in or latch out receive or out-

put data respectively.

iADDR

This Pin Must be Tied “Low” for Normal Operation.

This pin is internally pulled “High” with a 50k

Ω resistor.

MICROPROCESSOR INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

XRT86VL32IB Datasheet(PDF) 35 Page - Exar Corporation

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