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SC28L198 Datasheet(PDF) 43 Page - NXP Semiconductors |
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SC28L198 Datasheet(HTML) 43 Page - NXP Semiconductors |
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43 / 56 page  Philips Semiconductors Product specification SC28L198 Octal UART for 3.3V and 5V supply voltage 1999 Jan 14 43 AC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL AND INDUSTRIAL (5V) VCC = 5.0 volts " 10%; TA = –40 to 85°C; unless otherwise specified SYMBOL FIG # PARAMETER LIMIT UNIT MIN TYP MAX Reset Timing tRES1 RESET pulse width 10 Sclk Bus Timing tAS A0–A7 setup time before Sclk C3 rising edge 10 2 ns tAH A0–A7 hold time after Sclk C3 rising edge 18 8 ns tCS CEN setup time before Sclk C1 high (Sync) 5 3 ns CEN setup time before Sclk C2 high (Async) 5 3 ns tCH CEN hold time after Sclk C3 high (Sync) 14 1 ½Sclk ns CEN hold time after Sclk C4 high (Async) 25 1 ½Sclk ns tSTP CEN high before next C2 to stop next cycle (Sync Mode)2 18 ns tRWS W–Rn setup time before Sclk C2 rising edge 5 ns tRWH W–Rn hold time after Sclk C3 rising edge 14 1 ½Sclk ns tDD Read cycle Data valid after Sclk C3 rising edge 12 25 ns tDF Read cycle data bus floating after CEN high (Sync) 10 16 ns Read cycle data bus floating after C4 end high (Async) 10 15 ns tDS Write cycle data setup time before Sclk C4 rising edge 25 14 ns tDH Write cycle data hold time after Sclk C4 rising edge 15 8 ns tRWD High time between CEN low (Async) 12 ½ Sclk ns I/O Port Pin Timing tPS I/O input setup time before Sclk C3 rising edge 18 4 ns tPH I/O input hold time after Sclk C4 rising edge 12 1 ns tPD I/O output valid from: Write Sclk C4 rising edge (write to IOPIOR) 32 50 ns Interrupt Timing tIR IRQN from: Internal interrupt source active bid Reset to IRQN inactive Write IMR (set or clear IMR bit)3 22 26 43 75 45 Sclk ns ns tDD IACKN cycle Data valid after Sclk C3 rising edge 12 25 ns Tx/Rx Clock Timing tRX RxC high or low time 15 8 ns FRX4 RxC frequency (16 X) (1 X) 0 0 16 1 Mhz Mhz tTX TxC high or low time 15 7 ns FTX4 TxC frequency (16 X) (1 X) 0 0 16 1 Mhz Mhz Transmitter Timing tTXD TxD output delay from TxC low 32 60 ns ttcs TxC output delay from TxD output data –15 4 15 ns Receiver Timing tRXS RxD data setup time to RxC high (data) 20 –4 ns tRXH RxD data hold time from RxC high (data) 20 6 ns tsSTRT RxD data low time for receiving a valid Start Bit 17/32 bit time |
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