SC28L198 datasheet(25/56 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L198

Octal UART for 3.3V and 5V supply voltage

1999 Jan 14

Note: This bit must be at a one (1) for the receiver to enter the

arbitration process. It is the fact that this bit is zero (0) when the

RxFIFO is empty that stops an empty FIFO from entering the

interrupt arbitration. Also note that the meaning if this bit is not quite

the same as the similar bit in the status register (SR).

ISR[0] – Transmitter Ready

The general function of this bit is to indicate that the TxFIFO has an

at least one empty space for data. The particular meaning of the bit

is controlled by MR0[5:4] indicates the TxFIFO may be loaded with

one or more characters. If MR0[5:4] = 00 (the default condition) this

bit will not set until the TxFIFO is empty – sixteen bytes available. If

the fill level of the TxFIFO is below the trigger level programmed by

the TxINT field of the Mode Register 0, this bit will be set. A one in

this position indicates that at least one character can be sent to the

TxFIFO. It is turned off as the TxFIFO is filled above the level

programmed by MR0[5:4. This bit turns on as the FIFO empties; the

RxFIFO bit turns on as the FIFO fills. This often a point of confusion

in programming interrupt functions for the receiver and transmitter

FIFOs.

Note: This bit must be at a one (1) for the transmitter to enter the

arbitration process. It is the fact that this bit is zero (0) when the

RxFIFO is full that stops a full FIFO from entering the interrupt

arbitration. Also note that the meaning if this bit is not quite the

same as the similar bit in the status register (SR).

Table 12. IMR – Interrupt Mask Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I/O Port change

of state

Receiver Watch-dog

Time–out

Address recogni-

tion event

Xon/off event

Set to 0

Change of

Break State

RxRDY inter-

rupt

TxRDY inter-

rupt

The programming of this register selects which bits in the ISR cause

an interrupt output. If a bit in the ISR is a ’1’ and the corresponding

bit in the IMR is a ’1’, the interrupt source is presented to the internal

interrupt arbitration circuits, eventually resulting in the IRQN output

being asserted (low). If the corresponding bit in the IMR is a zero,

the state of the bit in the ISR has no affect on the IRQN output.

IMR[7] – Controls if a change of state in the inputs equipped with

input change detectors will cause an interrupt.

IMR[6] – Controls the generation of an interrupt by the watch-dog

timer event. If set, a count of 64 idle bit times in the receiver will

begin interrupt arbitration.

IMR[5] – Enables the generation of an interrupt in response to

changes in the Address Recognition circuitry of the Special Mode

(multi-drop or wake–up mode).

IMR[4] – Enables the generation of an interrupt in response to

recognition of an in–band flow control character.

IMR[3] – Reserved

IMR[2] – Enables the generation of an interrupt when a Break

condition has been detected by the channel receiver.

IMR[1] – Enables the generation of an interrupt when servicing for

the RxFIFO is desired.

IMR[0] – Enables the generation of an interrupt when servicing for

the TxFIFO is desired.

Table 13. RxFIFO Receiver FIFO

Bit[10]

Bit[9]

Bit[8]

Bits [7:0]

Break

Received

Status

Framing

Error Sta-

tus

Parity

Error Sta-

tus

8 data bits

MSBs =0 for 7,6,5 bit

data

The FIFO for the receiver is 11 bits wide and 16 ”words” deep. The

status of each byte received is stored with that byte and is moved

along with the byte as the characters are read from the FIFO. The

upper three bits are presented in the STATUS register and they

change in the status register each time a data byte is read from the

FIFO. Therefor the status register should be read BEFORE the byte

is read from the RxFIFO if one wishes to ascertain the quality of the

byte

The forgoing applies to the ”character error” mode of status

reporting. See MR1[5] and ”RxFIFO Status” descriptions for ”block

error” status reporting. Briefly ”Block Error” gives the accumulated

error of all bytes received in the RxFIFO since the last “Reset Error”

command was issued. (CR = x’04)

Table 14. TxFIFO – Transmitter FIFO

Bits 7:0

8 data bits. MSBs set to 0 for 7, 6, 5 bit data

The FIFO for the transmitter is 8 bits wide by 16 bytes deep. For

character lengths less than 8 bits the upper bits will be ignored by

the transmitter state machine and thus are effectively discarded.

Table 15. BCRBRK – Bidding Control Register –

Break Change

Bits 7:3

Bits 2:0

Reserved

MSB of break change interrupt bid

This register provides the 3 MSBs of the Interrupt Arbitration number

for a break change interrupt.

Table 16. BCRCOS – Bidding Control Register –

Change of State

Bits 7:3

Bits 2:0

Reserved

MSB of a COS interrupt bid

Read as x’0

This register provides the 3 MSBs of the Interrupt Arbitration number

for a Change of State, COS, interrupt.

Table 17. BCRx – Bidding Control Register – Xon

Bits 7:3

Bits 2:0

Reserved

MSB of an Xon/Xoff interrupt bid

This register provides the 3 MSBs of the Interrupt Arbitration number

for an Xon/Xoff interrupt.

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