SC28L198 datasheet(24/56 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L198

Octal UART for 3.3V and 5V supply voltage

1999 Jan 14

This bit is set when the ’with parity’ or ’force parity’ mode is

programmed and the corresponding character in the FIFO was

received with incorrect parity. In the special ’wake up mode’, the

parity error bit stores the received A/D bit.

SR[4] – Overrun Error (OE)

This bit, when set, indicates that one or more characters in the

received data stream have been lost. It is set upon receipt of a new

character when the RxFIFO is full and a character is already in the

receive shift register waiting for an empty FIFO position. When this

occurs, the character in the receive shift register (and its break

detect, parity error and framing error status, if any) is lost. This bit is

cleared by a reset error status command.

SR[3] – Transmitter Empty (TxEMT)

This bit is set when the transmitter underruns, i.e., both the TxFIFO

and the transmit shift register are empty.

It is set after transmission of the last stop bit of a character, if no

character is in the TxFIFO awaiting transmission. It is reset when

the TxFIFO is loaded by the CPU, or when the transmitter is

disabled.

SR[2] – Transmitter Ready (TxRDY)

This bit, when set, indicates that the TxFIFO is ready to be loaded

with a character. This bit is cleared when the TxFIFO is loaded by

the CPU and is set when the last character is transferred to the

transmit shift register. TxRDY is reset when the transmitter is

disabled and is set when the transmitter is first enabled, e.g.,

characters loaded in the TxFIFO while the transmitter is disabled will

not be transmitted.

SR[1] – RxFIFO Full (RxFULL)

This bit is set when a character is transferred from the receive shift

become full, i.e., all sixteen RxFIFO positions are occupied. It is

reset when the CPU reads the RxFIFO and that read leaves one

empty byte position. If a character is waiting in the receive shift

second read of the RxFIFO since the waiting character is

immediately loaded to the RxFIFO.

SR[0] – Receiver Ready (RxRDY)

This bit indicates that a character has been received and is waiting

in the RxFIFO to be read by the CPU. It is set when the character is

transferred from the receive shift register to the RxFIFO and reset

when the CPU reads the RxFIFO, and no more characters are in the

RxFIFO.

Table 11. ISR – Interrupt Status Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I/O Port

change of

state

Receiver

Watch-dog

Time–out

Address recogni-

tion event

Xon/off

event

Always 0

Change of

Break State

RxRDY

Receiver has entered

arbitration process

TxRDY

Transmitter has entered

arbitration process

This register provides the status of all potential interrupt sources for

a UART channel. When generating an interrupt arbitration value,

the contents of this register are masked by the interrupt mask

the IMR is also a ’1’, interrupt arbitration for this source will begin. If

the corresponding bit in the IMR is a zero, the state of the bit in the

ISR can have no affect on the IRQN output. Note that the IMR may

or may not mask the reading of the ISR as determined by MR1[6].

If MR1[6] is cleared, the reset and power on default, the ISR is read

without modification. If MR1[6] is set, the a read of the ISR gives a

value of the ISR ANDed with the IMR.

ISR[7] – Input Change of State

This bit is set when a change of state occurs at the I/O1 or I/O0

input pins. It is reset when the CPU reads the Input Port Register,

IPR.

ISR[6] Watch-dog Time–out

This bit is set when the receiver’s watch-dog timer has counted

more than 64 bit times since the last RxFIFO event. RxFIFO events

are a read of the RxFIFO or GRxFIFO, or the push of a received

character into the FIFO. The interrupt will be cleared automatically

upon the push of the next character received or when the RxFIFO or

GRxFIFO is read. The receiver watch-dog timer is included to allow

detection of the very last characters of a received message that may

be waiting in the RxFIFO, but are too few in number to successfully

initiate an interrupt. Refer to the watch-dog timer description for

details of how the interrupt system works after a watch-dog

time–out.

ISR[5] – Address Recognition Status Change

This bit is set when a change in receiver state has occurred due to

an Address character being received from an external source and

comparing to the reference address in ARCR. The bit and interrupt

is negated by a write to the CR with command x11011, Reset

Address Recognition Status.

ISR[4] – Xon/Xoff Status Change

This bit is set when an Xon/Xoff character being received from an

external source. The bit is negated by a read of the channel Xon

Interrupt Status Register, XISR.

ISR[3] – Reserved Always reads a 0

ISR[2] – Change in Channel Break Status

This bit, when set, indicates that the receiver has detected the

beginning or the end of a received break. It is reset when the CPU

issues a reset break change interrupt command via the CR.

ISR[1] – Receiver Ready

The general function of this bit is to indicate that the RxFIFO has

data available. The particular meaning of this bit is programmed by

MR2[3:2]. If programmed as receiver ready(MR2[3:2] = 00), it

indicates that at least one character has been received and is

waiting in the RxFIFO to be read by the host CPU. It is set when the

character is transferred from the receive shift register to the RxFIFO

and reset when the CPU reads the last character from the RxFIFO.

If MR2[3:2] is programmed as FIFO full, ISR[1] is set when a

character is transferred from the receive holding register to the

RxFIFO and the transfer causes the RxFIFO to become full, i.e. all

sixteen FIFO positions are occupied. It is reset when ever RxFIFO

is not full. If there is a character waiting in the receive shift register

because the FIFO is full, the bit is set again when the waiting

character is transferred into the FIFO.

The other two conditions of these bits, 3/4 and half full operate in a

similar manner. The ISR[1] bit is set when the RxFIFO fill level

meets or exceeds the value; it is reset when the fill level is less.

See the description of the MR2 register.

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