SC28L198 datasheet(16/56 Pages) PHILIPS

16 / 56 page

Philips Semiconductors

Product specification

SC28L198

Octal UART for 3.3V and 5V supply voltage

1999 Jan 14

While in this mode, the receiver continuously looks at the received

data stream, whether it is enabled or disabled. If disabled, it sets

the RxRDY status bit and loads the character into the RxFIFO if the

received A/D bit is a one, but discards the received character if the

received A/D bit is a zero. If the receiver is enabled, all received

characters are transferred to the CPU via the RxFIFO. In either

case, the data bits are loaded into the data FIFO while the A/D bit is

loaded into the status FIFO position normally used for parity error

(SR[5]). Framing error, overrun error, and break detect operate

normally whether or not the receiver is enabled.

Automatic operation, Wake Up & Doze

The automatic configuration for this mode uses on-board

comparators to examine incoming address characters. Each UART

channel may be assigned a unique address character. See the

address register map and the description of the Address

Recognition Character Register (ARCR). The device may be

programmed to automatically awaken a sleeping receiver and/or

disable an active receiver based upon address characters received.

The operation of the basic receiver is the same as described above

for the default mode of wake–up operation except that the CPU

need not be interrupted to make a change in the receiver status.

Three bits in the Mode Register 0, (MR0), control the address

recognition operation. MR0[6] controls the RxFIFO operation of the

received character; MR0[1:0] controls the wake up mode options. If

MR0[6] is set the address character will be pushed onto the

RxFIFO, otherwise the character will be discarded. (The charter is

stripped from the data stream) The MR0[1:0] bits set the options as

follows: A b’00 in this field, the default or power–on condition, puts

the device in the default (CPU controlled) wake up mode of

operation as described above. The auto–wake mode, enabled if

MR0[0] is set, will cause the dedicated comparators to examine

each address character presented by the receiver. If the received

character matches the reference character in ARCR, the receiver

will be enabled and all subsequent characters will be FIFOed until

another address event occurs or the host CPU disables the receiver

explicitly. The auto doze mode, enabled if MR0[1] is set, will

automatically disable the receiver if an address is received that does

not match the reference character in the ARCR.

The UART channel can present the address recognition event to the

interrupt arbiter for IRQN generation. The IRQN generation may be

masked by setting bit 5 of the Interrupt Mask Register, IMR. The bid

level of an address recognition event is controlled by the Bidding

Control Register, BCRA, of the channel.

Note: To ensure proper operation, the host CPU must clear any

pending Address Recognition interrupt before enabling a disabled

receiver operating in the Special or Wake–up mode. This may be

accomplished via the CR commands to clear the Address Interrupt

or by resetting the receiver.

Xon/Xoff Operation

Receiver Mode

Since the receiving FIFO resources in the Octal UART are limited,

some means of controlling a remote transmitter is desirable in order

to lessen the probability of receiver overrun. The Octal UART

provides two methods of controlling the data flow. A hardware

assisted means of accomplishing control, the so–called out–of–band

flow control, and an in–band flow control method.

The out–of–band flow control is implemented through the

CTSN–RTSN signaling via the I/O ports. The operation of these

hardware handshake signals is described in the receiver and

transmitter discussions.

In–band flow control is a protocol for controlling a remote transmitter

by embedding special characters within the message stream, itself.

Two characters, Xon and Xoff, which do not represent normal

printable characters take on flow control definitions when the

Xon/Xoff capability is enabled. Flow control characters received

may be used to gate the channel transmitter on and off. This activity

is referred to as Auto–transmitter mode. To protect the channel

receiver from overrun, fixed fill levels (hardware set at 12

characters) of the RxFIFO may be employed to automatically insert

Xon/Xoff characters in the transmitter’s data stream. This mode of

operation is referred to as auto–receiver mode. Commands issued

by the host CPU via the CR can simulate all these conditions.

Auto–transmitter mode

When a channel receiver pushes an Xoff character into the RxFIFO,

the channel transmitter will finish transmission of the current

character and then stop transmitting. A transmitter so idled can be

restarted by the receipt of an Xon character by the receiver, or by a

hardware or software reset. The last option results in the loss of the

un–transmitted contents of the TxFIFO. When operating in this

mode the Command Register commands for the transmitter are not

effective.

While idle data may be written to the TxFIFO and it continues to

present its fill level to the interrupt arbiter and maintains the integrity

of its status registers.

Use of ’00’ as an Xon/Xoff character is complicated by the Receiver

break operation which pushes a ’00’ character on the RxFIFO. The

Xon/Xoff character detectors do not discriminate this case from an

Xon/Xoff character received through the RxD pin.

Note: To be recognized as an Xon or Xoff character, the receiver

must have room in the RxFIFO to accommodate the character. An

Xon/Xoff character that is received resulting in a receiver overrun

does not effect the transmitter nor is it pushed into the RxFIFO,

regardless of the state of the Xon/Xoff transparency bit, MR0(7).

Note: Xon /Xoff characters

The Xon/Xoff characters with errors will be accepted as valid. The

user has the option sending or not sending these characters to the

FIFO. Error bits associated with Xon/Xoff will be stored normally to

the receiver FIFO.

The channel’s transmitter may be programmed to automatically

transmit an Xoff character without host CPU intervention when the

RxFIFO fill level exceeds a fixed limit (12). In this mode, it will

conversely transmit an Xon character when the RxFIFO level drops

below a second fixed limit (8). A character from the TxFIFO that has

been loaded into the TxD shift register will continue to transmit.

Character(s) in the TxFIFO that have not been popped are

unaffected by the Xon or Xoff transmission. They will be transmitted

after the Xon/Xoff activity concludes.

If the fill level condition that initiates Xon activity negates before the

flow control character can begin transmission, the transmission of

the flow control character will not occur, i.e. either of the following

sequences may be transmitted depending on the timing of the FIFO

level changes with respect to the normal character times:

Character

Xoff

Xon

Character

Hardware keeps track of Xoff characters sent that are not rescinded

by an Xon. This logic is reset by writing MR0(3) to ’0’. If the user

drops out of Auto–receiver mode while the XISR shows Xon as the

last character sent, the Xon/Xoff logic will not automatically send the

negating Xon.

Host mode

When neither the auto–receiver nor auto–transmitter modes are set,

the Xon/Xoff logic is operating in the host mode. In host mode, all

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