SC28L198 datasheet(23/56 Pages) PHILIPS

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Philips Semiconductors

Product specification

SC28L198

Octal UART for 3.3V and 5V supply voltage

1999 Jan 14

mechanism to initialize all the Xoff Character registers to a

default value with one write. Execution of this command

is immediate and does not effect the timing of subsequent

host I/O operations.

10110

Xoff resume command (CRXoffre; not active in

“Auto-Transmit Mode”). A command to cancel a previous

Host Xoff command. Upon receipt, the channel’s

transmitter will transfer a character, if any, from the

TxFIFO and begin transmission.

10111

Host Xoff command (CRXoff). This command allows tight

host CPU control of the flow control of the channel

transmitter. When interrupted for receipt of an Xoff

character by the receiver, the host may stop transmission

of further characters by the channel transmitter by issuing

the Host Xoff command. Any character that has been

transferred to the TxD shift register will complete its

transmission, including the stop bit.

11000

Cancel Host transmit flow control command. Issuing this

command will cancel a previous transmit command if the

flow control character is not yet loaded into the TxD Shift

or if its transmission has already begun, then this

command has no effect.

11001–11011

Reserved

11011 Reset Address Recognition Status. This command clears the

interrupt status that was set when an address character

was recognized by a disabled receiver operating in the

special mode.

11100–11101

Reserved

11110

Resets all UART channel registers. This command

provides a means to zero all the UART channels that are

not reset to x’00 by a reset command or a hardware reset.

11111

Reserved for channels b-h, for channel a: executes a chip

wide reset. Executing this command in channel a is

equivalent to a hardware reset with the RESETN pin.

Executing in channel b-h, has no effect.

Table 9. Command Register Code

Commands x’12, x13, x’14, x’15, x’1f (marked with*) are global and exist only in channel A’s register space.

Channel Command

Code

Channel

Command

Channel Command

Code

Channel

Command

CR[7:3]

Description

CR[7:3]

Description

00000

NOP

10000

Transmit Xon

00001

Reserved

10001

Transmit Xoff

00010

Reset Receiver

10010

Gang Write Xon Character Registers *

00011

Reset Transmitter

10011

Gang Write Xoff Character Registers *

00100

Reset Error Status

10100

Gang Load Xon Character Registers DC1 *

00101

Reset Break Change Interrupt

10101

Gang Load Xoff Character Registers DC3 *

00110

Begin Transmit Break

10110

Xoff Resume Command

00111

End Transmit Break

10111

Host Xoff Command

01000

Assert RTSN (I/O2 or I/O1)

11000

Cancel Transmit X Char command

01001

Negate RTSN (I/O2 or I/O1)

11001

Reserved

01010

Set time–out mode on

11010

Reserved

01011

Reserved

11011

Reset Address Recognition Status

01100

Set time–out mode off

11100

Reserved

01101

Block Error Status configure

11101

Reserved

01110

Reserved

11110

Reset All UART channel registers

01111

Reserved

11111

Reset Device *

Table 10. SR – Channel Status Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Received

Break

Framing Error

Parity

Error

Overrun Error

TxEMT

TxRDY

RxFULL

RxRDY

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

0 – No

1 – Yes

SR[7] – Received Break

This bit indicates that an all zero character of the programmed

length has been received without a stop bit. Only a single FIFO

position is occupied when a break is received; further entries to the

FIFO are inhibited until the RxD line returns to the marking state for

at least one half bit time (two successive edges of the internal or

external 1x clock). When this bit is set, the change in break bit in

the ISR (ISR[2]) is set. ISR[2] is also set when the end of the break

condition, as defined above, is detected. The break detect circuitry

is capable of detecting breaks that originate in the middle of a

received character. However, if a break begins in the middle of a

character, it must last until the end of the next character in order for

it to be detected.

SR[6] – Framing Error (FE)

This bit, when set, indicates that a stop bit was not detected when

the corresponding data character in the FIFO was received. The

stop bit check is made in the middle of the first stop bit position.

SR[5] – Parity Error (PE)

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