RT9470 datasheet(32/50 Pages) RICHTEK

32 / 50 page

RT9470/D

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS9470/D-02

October 2023

Application Information

Richtek’s component specification does not include the following information in the Application Information section.

Thereby no warranty is given regarding its validity and accuracy. Customers should take responsibility to verify their

own designs and reserve suitable design margin to ensure the functional suitability of their components and systems.

Power Up

⚫

Power-On-Reset (POR)

The device powers internal bias circuits from the

higher voltage of VBUS and VBAT. When VBUS

rises above 1.8V or VBAT rises above VBAT_UVLO,

I2C interface is ready for communication and all the

registers are reset to default value.

⚫

Device Power Up from Battery Only

When only Battery is present and VBAT above

VBAT_DPL_RISE, the BATFET turns on to connect

VBAT to VSYS. The REGN stays off to minimize the

quiescent current. The low quiescent current on

VBAT and low RDS(ON) of BATFET minimize device

power consumption and conduction loss maximum

battery run life.

The device always monitors the discharge current

through BATFET (Battery Supply Mode). When the

system

overloaded

shorted

(IBAT

IBATFET_OCP),

the

device

turns

off

BATFET

immediately and sets BATFET_DIS = 1 to enter

Shipping Mode until VBUS plugs in again or uses the

methods

exit

Shipping

Mode

re-enable

BATFET.

⚫

Device Power Up from VBUS

When the VBUS is plugged in, the power up

sequence is as listed :

Power up REGN LDO.

Poor Source Detection.

PORT_STAT Detection is based on PSEL or

input source type to set default Average Input

Current Regulation (AICR) register.

Minimum

Input

Voltage

Regulation

(MIVR)

setting.

Buck Converter Power-up.

⚫

Power-Up REGN LDO

The

REGN

LDO

supplies

the

High-side

and

Low-side MOSFET gate drive. The REGN also

provides bias to TS external resistor and pull-up rail

of STAT. The REGN is enabled when the below

conditions are valid :

VAC above VBAT + VSLEEP_RISE in buck mode

or enable OTG bit in boost mode.

After 220ms delay is completed when VAC

above VBAT + VSLEEP_RISE.

REGN LDO turns off when device in HZ mode,

sleep mode, VBUS over-voltage or OTG disable.

⚫

Poor Source Detection

After REGN powers up, the device checks the

current capability of the input source. The input

source has to meet following requirements to turn on

the buck converter.

VBUS below VAC_OVP_RISE.

VBUS above VBUS_BAD_ADP then pulling

IBADSRC (typical = 40mA).

When input source passes above conditions, the

ST_VBUS_GD and the FL_VBUS_GD turn to high

and INT pin is pulsed for interrupting the host. If

ST_VBUS_GD doesn’t turn to high, it repeats poor

source detection every 2 seconds.

⚫

VBUS Source Type Detection

After ST_VBUS_GD turns to high, the device runs

VBUS source type detection (RT9470D) or PSEL pin

status (RT9470). After detection is completed, the

ST_CHG_RDY and the FL_CHG_RDY turn to high

and INT pin is pulsed for interrupting the host.

Then the following registers are changed:

Average

Input

Current

Regulation

(AICR)

type detection or PSEL pin status automatically

if AUTO_AICR = 1.

RT9470 Datasheet(PDF) 32 Page - Richtek Technology Corporation

RT9470 Datasheet(HTML) 32 Page - Richtek Technology Corporation

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