STPMIC25APQR datasheet(47/145 Pages) STMICROELECTRONICS

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If the software has set both the RREQ_EN and SWOFF bits, the PMIC restarts automatically after the

POWER_DOWN sequence (transition K) and goes into the POWER_ON state. The RESTART_SR register is set

accordingly.

5.4.4.2

Turn-OFF condition triggered by a hard fault

Each hard-fault source has a hard-fault counter: see Table 24

Each time a hard-fault event occurs, a turn-off condition is triggered and it is managed by fail-safe management.

See Section 5.4.5

5.4.5

Fail-safe management

Each hard-fault source has an independent fail-safe counter that is incremented each time a hard-fault turn-off

condition occurs (see Table 24). If the counter value is below (or equal to) the max limit, then the PMIC restarts (=

power cycling on fault condition). Alternatively, if the counter is higher than the max limit, then the PMIC goes into

the FAIL_SAFE_LOCK state to avoid cyclic hard failures.

Sequence details:

When a turn-off condition is triggered by a hard-fault source (see Table 23):

•

The corresponding hard-fault counter is incremented (see Table 24): xxx_FLT_CNT ++

•

The FLT_TMR is loaded with the corresponding hard-fault duration and starts (see Table 24)

•

The PMIC switches to the POWER_DOWN sequence

•

Once the POWER_DOWN sequence ends:

–

If all counters xxx_FLT_CNT <= xxx_FLT_CNT_MAX then the PMIC goes into the CHECK&LOAD

state, then PMIC waits for a FLT_TMR timer expiration before restarting (see Table 29), then it goes

into POWER_UP, and then it goes in POWER_ON state. The corresponding bit in the RESTART_SR

status register is set.

–

Else if one of the counters xxx_FLT_CNT > xxx_FLT_CNT_MAX then PMIC goes into the

FAIL_SAFE_LOCK state. The corresponding bit in the TURN_OFF_SR status register is set. Even

when the FAIL_SAFE_LOCK is skipped, the PMIC waits for FLT_TMR expiration before restarting.

Table 24. Hard-fault fail-safe counters and waits before restarting timer

Source

Fail-safe counters

Max fault iteration (NVM shadow

Wait before restart timer

duration FLT_TMR[x]

VINOK_Fall

VIN_FLT_CNT[3:0]

VIN_FLT_CNT_MAX[3:0]

tVINOK_Fall

PONKEYn long press

PKEY_FLT_CNT[3:0]

PKEY_FLT_CNT_MAX[3:0]

Thermal shutdown

TSHDN_FLT_CNT[3:0]

TSHDN_FLT_CNT_MAX[3:0]

tTSHDN_DLY

Overcurrent protection

(OCP)

OCP_FLT_CNT[3:0]

OCP_FLT_CNT_MAX[3:0]

tHICCUP_DLY

Watchdog

WDG_FLT_CNT[3:0]

WDG_FLT_CNT_MAX[3:0]

Notes:

1- When a counter (xxx_FLT_CNT[3:0]) reaches 0xF, all the next counter increments keep the counter value at

0xF (and not restart to 0). This allows for infinite PMIC restart iterations to be set when xxx_FLT_CNT_MAX[3:0]

is set to 0xF.

2- Setting 0 in xxx_FLT_CNT_MAX makes the PMIC go into the FAIL_SAFE_LOCK state after the first

corresponding turn-off hard-fault condition (PMIC restarts 0 time).

3- Setting 0xF in xxx_FLT_CNT_MAX makes the PMIC always restart after any corresponding urn-off fault

condition as highlighted above in Note 1 (PMIC restarts indefinitely).

4- Programming the NVM with tHICCUP_DLY =‘0’ means no wait before restart.

5.4.5.1

Hard-fault counters reset and auto-reset

To avoid reaching the FAIL_SAFE_LOCK state due to isolated turn-off hard-fault conditions, all counters can be

reset automatically when no turn-off hard-fault condition occurs in RST_FTL_CNT_TMR timer duration. (See

Table 25 for timer duration NVM settings):

STPMIC25

Feature descriptions

DS14278 - Rev 3

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