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STPMIC25APQR Datasheet(PDF) 57 Page - STMicroelectronics

Part # STPMIC25APQR
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
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STPMIC25APQR Datasheet(HTML) 57 Page - STMicroelectronics

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5.4.10.1
Frequency spreading for buck converters
Electromagnetic interference (EMI) is an issue prevalent to DC-DC converters, as these signals can cause
disturbances to the system at large.
There are many proposed solutions to mitigate EMI, but STPMIC25 is focused on spread spectrum frequency
modulation (SSFM). SSFM is a way to utilize PWM technology by randomly varying the switching frequency
within a set range of 10 to 20% centered at the desired average 2 MHz switching frequency. This works to
eliminate harsh and potentially disastrous peaks at the switching frequency.
5.5
Programming
5.5.1
I²C interface
The I²C interface works in slave mode. It supports both standard and fast modes with a data rate up to 400 Kb/s.
It also supports fast mode plus (Fm+) with a data rate up to 1 Mb/s that is a suitable frequency for DVS
operations.
5.5.1.1
Device ID
There is a device ID system to address the STPMIC25.
The address is stored in the NVM_I²C_ADDR_SHR[6:0] shadow register bit field. The hard coded I²C default
address defined in the NVM is 0x33.
Table 28. Device ID format
b7
b6
b5
b4
b3
b2
b1
b0
AddID6
AddID5
AddID4
AddID3
AddID2
AddID1
AddID0
R/W
5.5.1.2
Read/write operation
Each transaction is composed of a start condition followed by a packet number (8-bit long) representing either a
device ID plus R/W command, register address, or register data coming to/from the slave.
Table 28 An acknowledgment is needed after each packet. This acknowledgment is given by the receiver of the
packet. Transaction examples are given in Table 29 and Table 30. Multi-read and multi-write operations are
supported.
Table 29. Register address format
b7
b6
b5
b4
b3
b2
b1
b0
RegAdd7
RegAdd6
RegAdd5
RegAdd4
RegAdd3
RegAdd2
RegAdd1
RegAdd0
Table 30. Register data format
b7
b6
b5
b4
b3
b2
b1
b0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
Figure 20. I²C read operation
STPMIC25
Feature descriptions
DS14278 - Rev 3
page 57/145



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