STPMIC25APQR datasheet(58/145 Pages) STMICROELECTRONICS

58 / 145 page

Figure 21. I²C write operation

5.5.2

Non-volatile memory (NVM)

The PMIC's built-in non-volatile memory provides a high flexibility to support a wide range of applications.

Its write management through I²C allows for the customization of the PMIC directly in final applications during

product development and mass production.

The NVM read operation is performed automatically in the INIT&LOAD state and in the CHECK&LOAD state to

set control registers with default values and configure the POWER_UP and POWER_DOWN sequence.

The NVM write operation can be performed several times (NVMEND cycles max) during application development

debugging procedures. Once the final settings have been defined, these can be written in the NVM content of

each part mounted on the customer application that is written in the production line under a controlled

environment.

In addition, the PMIC supports the NVM CRC check (or checksum) to guarantee its content integrity. The CRC is

computed by the PMIC during an NVM write operation. After the NVM write, the user reads back the NVM content

to check that the content is OK (and implicitly that the computed CRC is valid). Then, each time the PMIC reads

the NVM (in the INIT&LOAD and in the CHECK&LOAD states) if the CRC is not OK, the PMIC does not start up.

5.5.2.1

NVM read operation

The NVM read operation is fully managed by the PMIC.

For each read operation, the PMIC automatically loads the NVM content into NVM shadow registers. It means

that shadow register content is a copy of NVM content.

When the PMIC power supply is connected (VIN > VINPOR_Rise), the PMIC state machine goes into the

INIT&LOAD state (see Section 5.1). In this state, an NVM read operation is performed to check if the PMIC can

start up automatically, depending on the AUTO_TURN_ON NVM bit value.

If the AUTO_TURN_ON bit is not set, the PMIC goes into the OFF state; or, the PMIC goes into the

CHECK&LOAD state and continues to POWER_UP automatically.

Before each POWER_UP sequence, the NVM read operation is performed in the CHECK&LOAD state. NVM

content is loaded into shadow registers and NVM content integrity is checked with CRC. Additionally, the PMIC

initializes BUCK and LDO control registers with values predefined in the NVM and it configures the POWER_UP

and POWER_DOWN sequence of regulators.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 58/145

STPMIC25APQR Datasheet(PDF) 58 Page - STMicroelectronics