STPMIC25APQR datasheet(49/145 Pages) STMICROELECTRONICS

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5.4.6

Power control management (PWRCTRLx)

PWRCTRL1, PWRCTRL2, and PWRCTRL3 are digital inputs controlled from an application processor (see

Section 5.3.5). They are dedicated to managing different application power modes or special regulator reset

features.

PWRCTRL1, PWRCTRL2, PWRCTRL3 can be independently muxed onto each regulator instance (BUCKx or

LDOx).

For example, BUCK1 may be controlled by PWRCTRL2, and BUCK2, BUCK7, and LDO8 can be controlled by

PWRCTRL1, and so on.

A regulator instance can be controlled from a single PWRCTRL signal.

For each regulator instance, a PWRCTRL input can be used either to:

•

Switch between the xxx_MAIN_CR register or the xxx_ALT_CR register of a regulator (where xxx is the

regulator instance)

–

The regulator behaves according to the selected xxx_MAIN_CR or xxx_ALT_CR register

•

Reset a regulator instance to its default value (from the NVM)

PWRCTRL1, PWRCTRL2, or PWRCTRL3 can be used to switch the PMIC state machine RUN to STANDBY (see

Table 21).

PWRCTRL1, PWRCTRL2, or PWRCTRL3 can be used to suspend the watchdog, typically when the AP is in low-

power mode.

The Figure 15 provides the logic circuitry principle showing:

•

How a buck converter is controlled from a PWRCTRLx

•

How the PMIC state machine is driven to switch between RUN <=> STANDBY states

Figure 15. PWRCTRLx logic circuitry principle (TO BE CONTROLLE BY DESIGN)

PWRCTRL1

PWRCTRL_SEL[1:0]

PWRCTRL1_POL

delay high

delay low

PWRCTRL_DLY_H[1:0]

PWRCTRL_DLY_L[1:0]

PWRCTRL_EN && !PWRCTRL_RST

BUCKxIN

BUCKx

(or LDOx)

DAC

HP/LP

REF

VOUT[6:0]

PREG_MODE

AND

DISABLEn

VLXx

VOUTx

PWRCTRL_RST && !PWRCTRL_EN

AND

rst_n_i

(internal PMIC register init)

to other regulators

PWRCTRLx pull-up, pull-down, Schmitt trigger

and deglitch not shown

PMIC

PWRCTRL2

PWRCTRL2_POL

PWRCTRL3

PWRCTRL3_POL

DELAYout

DELAYin

RSTn

STANDBY_PWRCTRL_SEL[1:0]

1 = RUN

0 = STANDBY

PMIC state machine

Christophe Belet

ST Microelectronics

BUCKx_ALT_CR

RSTn

christophe belet STM

BUCKx_MAIN_CR

WDG_PWRCTRL_SEL[1:0]

1 = RUN

0 = SUSPEND

WATCHDOG

PWRCTRL1_POL, PWRCTRL2_POL, and PWRCTRL3_POL bits set the polarity of PWRCTRL1, PWRCTRL2,

and PWRCTRL3, respectively. Those settings are applicable for all regulators (not linked to a single regulator).

PWRCTRLx_POL: polarity of PWRCTRLx signal (with x= 1,2,3): 0: active low; 1: active high.

See Table 26.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 49/145

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