STPMIC25APQR datasheet(95/145 Pages) STMICROELECTRONICS

95 / 145 page

6.5.6

LDOx MAIN mode control register (LDOx_MAIN_CR) (x = 2/5/6/7/8)

Table 59. LDOx_MAIN_CR

reserved

BYPASS

VOUT[4:0]

R/W

•

Address: 0x4F/0x58/0x5B/0x5E/0x61

•

Default: 0b0XXXXXXX where X depends on the value programmed in NVM

•

Description: LDO2/LDO5/LDO6/LDO7/LDO8 MAIN mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable, bypass mode, and set the voltage of the related LDO instance which is applied to the MAIN mode

(see Section 5.4.6

[7]

reserved

[6]

BYPASS: select bypass mode operation

0: LDOx operates in normal mode

1: LDOx operates in bypass mode

The default value is defined by the BYPASS bit of the NVM_LDOx_SHR NVM shadow register

[5:1]

VOUT[4:0]: LDOx output voltage settings. See Section 4.2.6

The default value is defined in the VOUT[4:0] bit field of NVM_LDOx_SHR NVM shadow registers

[0]

EN:

0: LDOx is disabled

1: LDOx is enabled

The default value is defined in the LDOx_RANK[2:0] bit field of the NVM_LDOs_RANK_SHR NVM shadow registers. If

LDOx_RANK[2:0] = 0, LDOx is disabled at power up; if LDOx_RANK[2:0] = y (with 6 > y > 0) LDOx is enabled at power

up at rank y (see Section 5.2)

STPMIC25

DS14278 - Rev 3

page 95/145

STPMIC25APQR Datasheet(PDF) 95 Page - STMicroelectronics