STPMIC25APQR datasheet(79/145 Pages) STMICROELECTRONICS

79 / 145 page

6.3.3

PONKEYn long key press control register (PKEY_LKP_CR)

Table 44. PKEY_LKP_CR

PKEY_LKP_OFF

PKEY_LKP_FSLS

reserved

PKEY_LKP_TMR[3:0]

R/W

•

Address: 0x12

•

Default: 0bXX00XXXX where X depends on the value programmed in the NVM

•

Description: PONKEYn long key press control register. This register is initialized to the default value in the

CHECK&LOAD state.

[7]]

PKEY_LKP_OFF: (see Section 5.4.4 )

0: no effect

1: A PONKEYn long key press triggers a turn-off condition

Default value is defined by NVM_PKEY_LKP_OFF NVM bit

[6]

PKEY_LKP_FSLS: (see Section 5.4.5.2 )

0: no effect

1: A PONKEYn long key press allows the PMIC to go from the FAIL_SAFE_LOCK state to the

OFF state

Default value is defined by the NVM_PKEY_LKP_FSLS NVM bit

[5:4]

reserved

[3:0]

PKEY_LKP_TMR[3:0]: PONKEYn long key press timer duration

0000: 1 s

0001: 2 s

0010: 3 s

0011: 4 s

0100: 5 s

0101: 6 s

0110: 7 s

0111: 8 s

1000: 9 s

1001: 10 s

1010: 11 s

1011: 12 s

1100: 13 s

1101: 14 s

1110: 15 s

1111: 16 s

Default value is defined by the NVM_PKEY_LKP_TMR[1:0] NVM bit field

STPMIC25

DS14278 - Rev 3

page 79/145

STPMIC25APQR Datasheet(PDF) 79 Page - STMicroelectronics

STPMIC25APQR Datasheet(HTML) 79 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL