STPMIC25APQR datasheet(100/145 Pages) STMICROELECTRONICS

100 / 145 page

6.5.12

LDO3 ALTERNATE mode control register (LDO3_ALT_CR)

Table 65. LDO3_ALT_CR

SNK_SRC

BYPASS

VOUT[4:0]

R/W

•

Address: 0x53

•

Default: 0bXXXXXXXX where X depends on the value programmed in the NVM

•

Description: LDO3 ALTERNATE mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable, bypass mode or SNK_SRC mode, and set the voltage of LDO3, which is applied to the

ALTERNATE mode (see Section 5.4.6).

[7]

SNK_SRC: select sink/source mode operation (see Section 4.2.3)

0: LDO3 operates in sink/source mode

1: LDO3 operates in sink/source mode

The default value is the same as LDO3_MAIN_CR

Note: SNK_SRC bit has a higher priority than the BYPASS mode operation (in case both bits are set at the same time)

[6]

BYPASS: select bypass mode operation

0: LDO3 operates in normal mode

1: LDO3 operates in bypass mode

The default value is the same as LDO3_MAIN_CR

[5:1]

VOUT[4:0]: LDO3 output voltage settings. See Section 4.2.6

The default value is the same as LDO3_MAIN_CR

[0]

EN:

0: LDO3 is disabled

1: LDO3 is enabled

The default value is the same as LDO3_MAIN_CR

STPMIC25

DS14278 - Rev 3

page 100/145

STPMIC25APQR Datasheet(PDF) 100 Page - STMicroelectronics