STPMIC25APQR datasheet(103/145 Pages) STMICROELECTRONICS

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6.5.15

REFDDR MAIN mode control register (REFDDR_MAIN_CR)

Table 68. REFDDR_MAIN_CR

reserved

R/W

•

Address: 0x64

•

Default: 0b0000000X where X depends on the value programmed in the NVM

•

Description: REFDDR MAIN mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable REFDDR, which is applied to the MAIN mode (see Section 5.4.6).

[7:1]

reserved

[0]

EN:

0: REFDDR is disabled

1: REFDDR is enabled

The default value is defined in the REFDDR_RANK[2:0] bit field of the NVM_LDOs_RANK_SHR5 NVM shadow

registers. If REFDDR_RANK[2:0] = 0, REFDDR is disabled at power-up. If REFDDR_RANK[2:0] = y (with 6 > y > 0),

REFDDR is enabled at power-up at rank y (see Section 5.2)

6.5.16

REFDDR ALTERNATE mode control register (REFDDR_ALT_CR)

Table 69. REFDDR_ALT_CR

reserved

R/W

•

Address: 0x65

•

Default: 0b0000000X where X depends on the value programmed in the NVM

•

Description: REFDDR ALTERNATE mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable REFDDR, which is applied to the ALTERNATE mode (see Section 5.4.6).

[7:1]

reserved

[0]

EN:

0: REFDDR is disabled

1: REFDDR is enabled

The default value is the same as REFDDR_MAIN_CR

STPMIC25

DS14278 - Rev 3

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