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STPMIC25APQR Datasheet(PDF) 107 Page - STMicroelectronics

Part # STPMIC25APQR
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPMIC25APQR Datasheet(HTML) 107 Page - STMicroelectronics

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6.6.5
Interrupt pending register 4 (INT_PENDING_R4)
Table 74. INT_PENDING_R4
7
6
5
4
3
2
1
0
LDO8_OCP
LDO7_OCP
LDO6_OCP
LDO5_OCP
LDO4_OCP
LDO3_OCP
LDO2_OCP
LDO1_OCP
R
R
R
R
R
R
R
R
•
Address: 0x73
•
Default: 0x00
•
Description: Interrupt mask register 1 to 4 (see Section 6.6.1).
This register is reset to the default value as long as RSTn is asserted.
For all bits:
0: interrupt not pending
1: interrupt pending
[7]
LDO8_OCP: Overcurrent detected on LDO8
[6]
LDO7_OCP: Overcurrent detected on LDO7
[5]
LDO6_OCP: Overcurrent detected on LDO6
[4]
LDO5_OCP: Overcurrent detected on LDO5
[3]
LDO4_OCP: Overcurrent detected on LDO4
[2]
LDO3_OCP: Overcurrent detected on LDO3
[1]
LDO2_OCP: Overcurrent detected on LDO2
[0]
LDO1_OCP: Overcurrent detected on LDO1
6.6.6
Interrupt clear registers (INT_CLEAR_Rx) (x = 1 to 4)
Table 75. INT_CLEAR_Rx
7
6
5
4
3
2
1
0
Same as INT_PENDING_Rx
W/R0
W/R0
W/R0
W/R0
W/R0
W/R0
W/R0
W/R0
•
Address: 0x74/0x75/0x76/0x77
•
Default: 0x00
•
Description: Interrupt clear registers 1 to 4 (see Section 6.6.1).
Writing 1 clears the corresponding interrupt bit in INT_PENDING_Rx. The bit is self-cleared, and always reads 0.
STPMIC25
Register descriptions
DS14278 - Rev 3
page 107/145



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