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STPMIC25APQR Datasheet(PDF) 110 Page - STMicroelectronics |
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STPMIC25APQR Datasheet(HTML) 110 Page - STMicroelectronics |
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110 / 145 page  6.7.2 NVM control register (NVM_CR) Table 80. NVM_CR 7 6 5 4 3 2 1 0 reserved reserved reserved reserved reserved reserved NVM_CMD[1:0] R R R R R R R/W R/W • Address: 0x8F • Default: 0x00 • Description: NVM control register. [7:2] reserved [1:0] NVM_CMD[1:0]: NVM controller command bits to control the NVM operation on the NVM shadow register bits. 00: No operation 01: Program (write shadow register to the NVM) 10: Read (load NVM content into shadow register) 11: No operation STPMIC25 Register descriptions DS14278 - Rev 3 page 110/145 |
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