STPMIC25APQR datasheet(50/145 Pages) STMICROELECTRONICS

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Table 26. PWRCTRLx polarity truth table

PWRCTRLx input level

PWRCTRLx_POL

PWRCTRLx logic level

Active

Inactive

Active

Note:

x is the instance number of the PWRCTRL pin.

STANDBY_PWRCTRL_SEL[1:0]: State machine control source selection for state transition RUN <=> STANDBY

when the PMIC is in the POWER_ON state (see Section 5.1).

WDG_PWRCTRL_SEL[1:0]: Watchdog control source selection. When PWRCTRLx is active, the watchdog timer

is suspended. When PWRCTRLx is inactive, the watchdog timer is running (if watchdog is enabled) (see

Section 5.4.10).

Note: There is one instance of the following registers per regulator instance:

PWRCTRL_SEL[1:0]: BUCKx control/reset source selection.

PWRCTRL_DLY_H[1:0]: BUCKx control/reset source shift delay from low to High level (typically to perform the

power ON sequence between different regulators; driven by a PWRCTRL signal). 0 = no delay; 1 = 1.5 ms delay;

2 = 3 ms delay; and 3 = 6 ms delay.

PWRCTRL_DLY_L[1:0]: BUCKx control/reset source shift delay from high to Low level (typically to emulate the

power OFF sequence between different regulators; driven by a PWRCTRL signal). 0 = no delay; 1 = 1.5 ms

delay; 2 = 3 ms delay; and 3 = 6 ms delay.

PWRCTRL_EN: BUCKx control source enable. 0: disable, 1: enable. When enabled, BUCKx is controlled from a

PWRCTRL signal:

•

If PWRCTRL is inactive, the BUCKx_MAIN_CR register is used to control BUCKx

•

If PWRCTRL is active, the BUCKx_ALT_CR register is used to control BUCKx

PWRCTRL_RST: BUCKx independent reset source enable. 0: disable, 1: enable. When enabled, BUCKx is reset

from a PWRCTRL signal. See Section 5.4.6.2 for details:

1. If PWRCTRL is active

2. BUCKx is disabled (forced by the DISABLEn signal in Figure 15)

3. The BUCKx_MAIN_CR and BUCKx_ALT_CR registers are reset to default value (the NVM default value is

reloaded in both registers).

4. If PWRCTRL is inactive, the BUCKx_MAIN_CR register is used to control BUCKx.

Notes:

1 - If both PWRCTRL_EN and PWRCTRL_RST are set by mistake, both the control source and independent

reset features are disabled (no effect).

2 - The above bit field descriptions are also applicable for LDOs by replacing BUCKx with LDOx.

Table 27. Regulator control truth table

PWRCTRLx logic level

PWRCTRL_RST

PWRCTRL_EN

Regulator control register

active or inactive

xxx_MAIN_CR

active

xxx_ALT_CR

inactive

xxx_MAIN_CR

active

xxx regulator disabled (OFF)

xxx_MAIN_CR & xxx_ALT_CR registers are reset to default value

inactive

xxx_MAIN_CR

active or inactive

xxx_MAIN_CR

Note:

: x is the instance number of the PWRCTRL pin; xxx is the instance name of a regulator.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 50/145

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