STPMIC25APQR datasheet(54/145 Pages) STMICROELECTRONICS

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Figure 18. Reset power-cycle sequence example

christophe belet

ST Microelectonics

POWER_DOWN

POWER_ON

RSTn

PMIC State

RANK1 (LDO1)

mask_reset

RANK3 (BUCK1/2)

RANK0 RANK5 RANK4 RANK3

RANK4 (LDO4)

RANK0 (BUCK6)

RST

Enable BUCK6

by I²C

CHECK&

LOAD

POWER_UP

RANK1 RANK2 RANK3

POWER_ON

RSTn asserted

by AP

RANK2 RANK1

RANK4 RANK5

RANK2 (BUCK4)

RSTn released

by PMIC

RSTn released

by AP

RST

(2)

(1)

(2)

7 ms ?

(1): RANK_DLY[1:0]

(2): RST_DLY[1:0]

For RANK_DLY and RST_DLY see Table 91

Settings related to the example in Figure 18:

LDO1 with mask_reset option set (LDOS_MRST_CR[LDO1_MRST] = 1), is not impacted by the reset power-

cycle.

BUCK1, BUCK2, BUCK4, and LDO4 are powered down and up at their respective ranks defined in the NVM.

BUCK6 is enabled by I2C. So, it is powered down first and not restarted (as not defined in the NVM to start).

mask_reset is valid once. It is cleared in the CHECK&LOAD state. So, it is cleared following a turn-OFF

condition, a VINPOR, and a RSTn assertion.

When RSTn is released by the application processor, the PMIC keeps RSTn asserted (the RSTn signal keeps

low) meaning that the application processor is kept in reset until the PMIC releases the RSTn signal.

5.4.8

Thermal protection

The PMIC implements a thermal protection to prevent overheating damage. PMIC junction temperature is

permanently monitored by an embedded thermal sensor.

The first level of thermal protection consists of an alarm sent by an interrupt to the application processor:

•

When Tj rises above the TWRN_Rise threshold, the PMIC generates an THW_RI interrupt

•

When Tj falls below the TWRN_Fall threshold, the PMIC generates an THW_FA interrupt

The application processor can manage to decrease the application activity load to decrease the application power

consumption. Alternatively, a second level of thermal protection may occur.

The second level of thermal protection consists of triggering a turn-OFF hard-fault condition:

•

When Tj rises above the TSHDN_Rise threshold, the PMIC generates a turn-OFF hard-fault condition, and

the thermal fail-safe counter is incremented (TSHDN_FLT_CNT ++):

–

If the thermal fail-safe counter reaches the maximum number of power cycles defined in the NVM

(TSHDN_FLT_CNT > TSHDN_FLT_CNT_MAX) then the PMIC goes into the FAIL_SAFE_LOCK

state.

–

Alternatively, when Tj falls below the TSHDN_Fall threshold and a tTSHDN_DLY delay ends, the PMIC

restarts.

See Section 5.4.5 for details about fail-safe counter management.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 54/145

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