STPMIC25APQR datasheet(32/145 Pages) STMICROELECTRONICS

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4.3.1

Buck converters' common features

Enable/Disable: each buck can be enabled or disabled independently (same behavior as LDO: see

Section 4.2.1)

VOUT voltage setting: output voltage can be set:

•

Automatically during a POWER_UP or POWER_DOWN sequence depending on the NVM settings.

•

By software (I²C access): setting the VOUT bit field in the related buck control register.

•

By PWRCTRLx pins state change: the BUCKx converter behaves according to BUCKx_MAIN_CR and

BUCKx_ALT_CR content setting. BUCKx_MAIN_CR or BUCKx_ALT_CR is selected by the PWRCTRL pin

allocated to BUCKx (see section Section 5.4.6 (PWRCTRLx)).

Forced PWM mode (CCM mode): each buck can be forced to work in PWM mode to keep a constant frequency

and low ripple.

HP/LP mode: each buck supports High Power (HP) mode and Low Power (LP) mode:

High Power mode (HP): buck converters work with maximum performance response.

Low Power mode (LP): the target of the LP mode is to decrease quiescent current. Buck converters work with

limited performance.

In LP mode, buck converters support max IOUT_LP_PEAK peak currents.

HP/LP and forced PWM modes are activated by two bits PREG_MODE [1:0] register as follows:

00: HP (or auto mode)

01: LP

10: Forced PWM (CCM)

11: reserved

Clock synchronization and clock phase shifting: in HP mode, when all buck converters work in a steady state

in CCM mode, they are synchronized with a clock and are shifted by 45° in the following order:

•

BUCK1

•

45°: BUCK4

•

90°: BUCK2

•

135°: BUCK5

•

180°: BUCK3

•

225°: BUCK6

•

270°: BUCK7

Note:

It is possible to force all buck converters' synchronization by 45° phase shifting by setting all buck converters in

forced CCM mode. This improves EMI and avoids peak current on the main power supply input source.

Frequency spreading: switching frequency spreading is supported to help manage EMC.

Dynamic voltage scaling (DVS): when the buck output voltage is increased/decreased dynamically by the

software, the buck output voltage (VOUT) is stepped up/down following the SRBK slew rate.

When a lower VOUT is set, part of the buck converter output energy is discharged from the output capacitor

following the SRBK slew rate, providing current back to the input supply capacitor. This operation improves the

total power efficiency.

STPMIC25

Power regulator descriptions

DS14278 - Rev 3

page 32/145

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