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STPMIC25APQR Datasheet(PDF) 75 Page - STMicroelectronics |
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STPMIC25APQR Datasheet(HTML) 75 Page - STMicroelectronics |
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75 / 145 page  6.2.12 Fail-safe counter status register 3 (FS_CNT_SR3) Table 40. FS_CNT_SR3 7 6 5 4 3 2 1 0 reserved reserved reserved reserved WDG_FLT_CNT[3:0] R R R R R R R R • Address: 0x0B • Default: 0x00 • Description: Fail-safe counters store the number of hard-fault occurrences. There is one fail-safe counter by hard fault source (see Section 5.4.5 ). FS_CNT_SR3 is reset in OFF state. [7:4] reserved [3:0] WDG_FLT_CNT[3:0]: number of occurrences triggered by watchdog hard-fault source. Note: When a counter (xxx_FLT_CNT[3:0]) reaches 0xF, all next counter increments keep the counter value at 0xF (and not restart to 0). STPMIC25 Register descriptions DS14278 - Rev 3 page 75/145 |
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