STPMIC25APQR datasheet(112/145 Pages) STMICROELECTRONICS

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6.8.2

NVM main control shadow register 2 (NVM_MAIN_CTRL_SHR2)

Table 82. NVM_MAIN_CTRL_SHR2

RANK_DLY[1:0]

RST_DLY[1:0]

NVM_PKEY_LKP_OFF

NVM_PKEY_LKP_FSLS

NVM_PKEY_LKP_TMR[1:0]

R/W

Address: 0x91

Default: Depends on the PMIC part number

Description: NVM main control shadow register 2.

[7:6]

RANK_DLY[1:0]: power-up/power-down step (RANK) duration:

00: 1.5 ms

01: 3 ms

10: 4.5 ms

11: 6 ms

(see Section 5.2)

[5:4]

RST_DLY[1:0]: RST release delay after POWER_UP sequence:

00: no delay

01: 1.5 ms

10: 3 ms

11: 6 ms

(see Section 5.2)

[3]

NVM_PKEY_LKP_OFF: PONKEYn long key press turn-off condition default value (see Section 5.4.4)

0: no effect

1: A PONKEYn long key press triggers a turn-off condition

[2]

NVM_PKEY_LKP_FSLS: PONKEYn long key press fail-safe lock state skipping default value (see Section 5.4.5.2)

0: no effect

1: A PONKEYn long key press allows the PMIC to go from the FAIL_SAFE_LOCK state to the OFF state

[1:0]

NVM_PKEY_LKP_TMR[1:0]: PONKEYn long key press timer duration default value

00: 2 s

01: 5 s

10: 10 s

11: 15 s

STPMIC25

DS14278 - Rev 3

page 112/145

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