STPMIC25APQR datasheet(111/145 Pages) STMICROELECTRONICS

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6.8

NVM shadow registers

All NVM shadow registers are reloaded from the NVM content in the INIT&LOAD state and in the CHECK&LOAD

state. Then mirror registers or mirror bit fields (in Section 6.3 and Section 6.5) are set to the default value.

6.8.1

NVM main control shadow register 1 (NVM_MAIN_CTRL_SHR1)

Table 81. NVM_MAIN_CTRL_SHR1

VINOK_HYST[1:0]

VINOK_RISE[1:0]

NVM_WDG_TMR_SET[1:0]

NVM_WDG_EN

AUTO_TURN_ON

R/W

•

Address: 0x90

•

Default: Depends on the PMIC part number

•

Description: NVM main control shadow register 1.

[7:6]

VINOK_HYST[1:0]: VINOK_HYST threshold voltage

00: 200 mV

01: 300 mV

10: 400 mV

11: 500 mV

[5:4]

VINOK_RISE[1:0]: VINOK_Rise threshold voltage

00: 3.1 V

01: 3.3 V

10: 3.5 V

11: 4.0 V

[3:2]

NVM_WDG_TMR_SET [1:0]: watchdog timer duration default value

00: 10 s

01: 20 s

10: 50 s

11: 100 s

[1]

NVM_WDG_EN: watchdog default value

0: Watchdog is disabled

1: Watchdog is enabled

[0]

AUTO_TURN_ON:

0: PMIC does not start automatically on VIN rising

1: PMIC starts automatically on VIN rising

STPMIC25

DS14278 - Rev 3

page 111/145

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