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STPMIC25APQR Datasheet(PDF) 113 Page - STMicroelectronics |
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STPMIC25APQR Datasheet(HTML) 113 Page - STMicroelectronics |
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113 / 145 page  6.8.3 NVM rank shadow register 1 (NVM_RANK_SHR1) Table 83. NVM_RANK_SHR1 7 6 5 4 3 2 1 0 reserved reserved BUCK2_RANK[2:0] BUCK1_RANK[2:0] R/W R/W R/W R/W R/W R/W R/W R/W • Address: 0x92 • Default: Depends on the PMIC part number • Description: NVM rank shadow register 1 (see section Section 5.2). [7:6] reserved [5:3] BUCK2_RANK[2:0]: 000: rank0 001: rank1 010: rank2 011: rank3 100: rank4 101: rank5 110: rank0 111: rank0 [2:0] BUCK1_RANK[2:0]: 000: rank0 001: rank1 010: rank2 011: rank3 100: rank4 101: rank5 110: rank0 111: rank0 6.8.4 NVM rank shadow register 2 (NVM_RANK_SHR2) Table 84. NVM_RANK_SHR2 7 6 5 4 3 2 1 0 reserved reserved BUCK4_RANK[2:0] BUCK3_RANK[2:0] R R R/W R/W R/W R/W R/W R/W • Address: 0x93 • Default: Depends on the PMIC part number • Description: NVM rank shadow register 2. Same bit field as section 6.7.3 NVM rank shadow register 1 (NVM_RANK_SHR1). STPMIC25 Register descriptions DS14278 - Rev 3 page 113/145 |
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