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STPMIC25APQR Datasheet(PDF) 119 Page - STMicroelectronics

Part # STPMIC25APQR
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPMIC25APQR Datasheet(HTML) 119 Page - STMicroelectronics

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6.8.14
NVM LDOx shadow register (NVM_LDOx_SHR) (x = 2/5/6/7/8)
Table 94. NVM_LDOx_SHR
7
6
5
4
3
2
1
0
reserved
BYPASS
VOUT[4:0]
reserved
R
R/W
R/W
R/W
R/W
R/W
R/W
R
•
Address: 0xA3/A5 to 0xA8
•
Default: Depends on the PMIC part number
•
Description: NVM LDO2/LDO5/LDO6/LDO7/LDO8 control shadow registers.
The contents of these registers are copied into LDOx_MAIN_CR and LDOx_ALT_CR in the CHECK&LOAD state
(see Section 4.2.6).
[7]
reserved
[6]
BYPASS: select default bypass mode operation:
0: LDOx operates in normal mode by default
1: LDOx operates in bypass mode by default
[5:1]
VOUT[4:0]: LDOx default output voltage settings. See Section 4.2.6.
[0]
reserved
6.8.15
NVM LDO3 control shadow register (NVM_LDO3_SHR)
Table 95. NVM_LDO3_SHR
7
6
5
4
3
2
1
0
reserved
BYPASS
VOUT[4:0]
reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
Address: 0xA4
•
Default: Depends on the PMIC part number
•
Description: NVM LDO3 control shadow register.
The content of this register is copied into LDO3_MAIN_CR and LDO3_ALT_CR in the CHECK&LOAD state (see
Section 4.2.6).
[7]
reserved
[6]
BYPASS: select default bypass mode operation:
0: LDOx operates in normal mode by default
1: LDOx operates in bypass mode by default
[5:1]
VOUT[4:0]: LDOx default output voltage settings. See Table 19.
[0]
reserved
STPMIC25
Register descriptions
DS14278 - Rev 3
page 119/145



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