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STPMIC25APQR Datasheet(PDF) 127 Page - STMicroelectronics

Part # STPMIC25APQR
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPMIC25APQR Datasheet(HTML) 127 Page - STMicroelectronics

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6.8.23
NVM fail-safe overcurrent protection shadow register 2 (NVM_FS_OCP_SHR2)
Table 103. NVM_FS_OCP_SHR2
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
•
Address: 0xB0
•
Default: Depends on the PMIC part number
•
Description: NVM fail-safe overcurrent protection shadow register 2 (see Section 5.4.9).
[7]
NVM_FS_OCP_LDO8: LDO8 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[6]
NVM_FS_OCP_LDO7: LDO7 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[5]
NVM_FS_OCP_LDO6: LDO6 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[4]
NVM_FS_OCP_LDO5: LDO5 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[3]
NVM_FS_OCP_LDO4: LDO4 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[2]
NVM_FS_OCP_LDO3: LDO3 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[1]
NVM_FS_OCP_LDO2: LDO2 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
[0]
NVM_FS_OCP_LDO1: LDO1 OCP management mode selection.
0: OCP Hiccup mode (Level 0)
1: OCP fail-safe PMIC turn-off (Level 1)
STPMIC25
Register descriptions
DS14278 - Rev 3
page 127/145



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