H838024 datasheet(325/697 Pages) RENESAS

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Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 283 of 652

REJ09B0042-0700

Table 9.11 shows the register configuration of timer G.

Table 9.11

Timer G Registers

Name

Abbr.

R/W

Initial Value

Address

Timer control register G

TMG

R/W

H'00

H'FFBC

Timer counter G

TCG

—

H'00

—

Input capture register GF

ICRGF

H'00

H'FFBD

Input capture register GR

ICRGR

H'00

H'FFBE

Clock stop register 1

CKSTPR1

R/W

H'FF

H'FFFA

9.5.2

Timer Counter G (TCG)

TCG7

TCG2

TCG1

TCG0

TCG6

TCG5

TCG4

TCG3

543210

0000000







Bit:

Initial value:

Read/Write:

TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by

bits CKS1 and CKS0 in TMG.

TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate

TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the

rising edge, falling edge, or both edges of the input capture input signal, according to the setting

made in TMG.

When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG in IRR2 is set to 1, and if

IENTG in IENR2 is 1, an interrupt request is sent to the CPU.

For details of the interrupt, see section 3.3, Interrupts.

TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.

Note: * An input capture signal may be generated when TMIG is modified.

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