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H838024 Datasheet(PDF) 328 Page - Renesas Technology Corp |
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H838024 Datasheet(HTML) 328 Page - Renesas Technology Corp |
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328 / 697 page  Section 9 Timers Rev. 7.00 Mar 10, 2005 page 286 of 652 REJ09B0042-0700 Bit 5—Timer Overflow Interrupt Enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE Description 0 TCG overflow interrupt request is disabled (initial value) 1 TCG overflow interrupt request is enabled Bit 4—Input Capture Interrupt Edge Select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request. Bit 4 IIEGS Description 0 Interrupt generated on rising edge of input capture input signal (initial value) 1 Interrupt generated on falling edge of input capture input signal Bits 3 and 2—Counter Clear 1 and 0 (CCLR1, CCLR0) Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges of the input capture input signal. Bit 3 CCLR1 Bit 2 CCLR0 Description 0 0 TCG clearing is disabled (initial value) 0 1 TCG cleared by falling edge of input capture input signal 1 0 TCG cleared by rising edge of input capture input signal 1 1 TCG cleared by both edges of input capture input signal |
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