H838024 datasheet(326/697 Pages) RENESAS

326 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 284 of 652

REJ09B0042-0700

Input Capture Register GF (ICRGF)

ICRGF7

ICRGF2

ICRGF1

ICRGF0

ICRGF6

ICRGF5

ICRGF4

ICRGF3

543210

0000000

RRR

Bit:

Initial value:

Read/Write:

ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is

detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,

IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.

For details of the interrupt, see section 3.3, Interrupts.

To ensure dependable input capture operation, the pulse width of the input capture input signal

must be at least 2

φ or 2φ

SUB (when the noise canceler is not used).

ICRGF is initialized to H'00 upon reset.

Input Capture Register GR (ICRGR)

ICRGR7

ICRGR2

ICRGR1

ICRGR0

ICRGR6

ICRGR5

ICRGR4

ICRGR3

543210

0000000

RRR

Bit:

Initial value:

Read/Write:

ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is

detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 0 at this time,

IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.

For details of the interrupt, see section 3.3, Interrupts.

To ensure dependable input capture operation, the pulse width of the input capture input signal

must be at least 2

φ or 2φ

SUB (when the noise canceler is not used).

ICRGR is initialized to H'00 upon reset.

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