H838024 datasheet(333/697 Pages) RENESAS

333 / 697 page

Section 9 Timers

Rev. 7.00 Mar 10, 2005 page 291 of 652

REJ09B0042-0700

b. Interval timer operation

When the TMIG bit in PMR1 is cleared to 0, timer G functions as an interval timer.

Following a reset, TCG starts counting on the

φ/64 internal clock. The input clock can be

selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments

on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set

to 1. If the OVIE bit in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if the IENTG bit

in IENR2 is 1, timer G sends an interrupt request to the CPU. For details of the interrupt, see

section 3.3, Interrupts.

Count Timing

TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four

internal clock sources (

φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch

clock (

φw).

Input Capture Input Timing

a. Without noise cancellation function

For input capture input, dedicated input capture functions are provided for rising and falling

edges.

Figure 9.11 shows the timing for rising/falling edge input capture input.

Input capture

input signal

Input capture

signal F

Input capture

signal R

Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)

H838024 Datasheet(PDF) 333 Page - Renesas Technology Corp