PM5316 datasheet(49/491 Pages) PMC

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

Pin Name

Type

No.

Function

TSLD1-4.

The TTOC Overhead Control register of the corresponding channel

contains the TSLD_SEL register bit used to select the section or

line DCC. The same register also contains the TSLD_VAL register

bit used to specify a value for the DCC not inserted via TSLD.

TSLD1-4 is sampled on the rising edge of TSLDCLK1-4.

9.7

Transmit Path AIS Insertion Signals

Pin Name

Pin Type

No.

Function

DPAISCK

Input

D27

The Drop bus path alarm indication clock signal (DPAISCK) provides

timing for system Drop path alarm indication signal (DPAIS).

DPAISCK is a clock of arbitrary phase and frequency within the limits

specified in the A.C. Timing section of this document.

Inputs DPAIS and DPAISFP are sampled on the rising edge of

DPAISCK.

DPAISFP

Input

B28

The active high Drop bus path alarm indication frame pulse signal

(DPAISFP) is used to identify the alignment of the DPAIS signal.

DPAISFP is set high to mark the path request of channel one’s the

first Drop bus STS-1 (STM-0/AU-3) stream or STS-3c (STM-1/AU-4)

stream. In the absence of a frame pulse, the device will maintain the

last alignment and wrap around on its own.

DPAISFP is sampled on the rising edge of DPAISCK.

DPAIS

Input

C27

The active high Drop bus path alarm indication signal (DPAIS) is a

timeslot multiplexed signal that controls the insertion of path alarm

indication signal (PAIS) on the Drop bus (DD[31:24], DD[23:16],

DD[15:8], DD[7:0]) on a per STS-1/STM-1(AU3) or STS-

3c/STM1(AU4)basis.

A high level on DPAIS during a specific timeslot forces the insertion

of the all-ones pattern into the corresponding SPE and the payload

pointer bytes (H1, H2, and H3) presented on the Drop bus. A high

during the first time slot of a channel carrying an STS-3c/STM-

1(AU4) stream will force the entire concatenated SPE to all-ones. A

high during the second or third time slot of a channel carrying an

STS-3c/STM-1(AU4) will have no effect.

Path AIS can also be inserted by setting the IPAIS control bit in the

RTAL Control register or in response to receive alarms by the RPPS

Path AIS Control #1 and #2 registers.

DPAIS may be enabled or disabled on a per slice basis via the

DPAIS_EN bit in the RPPS Path AIS Control register #1.

DPAIS is sampled on the rising edge of DPAISCK.

TPAISCK

Input

E26

The Transmit path alarm indication clock signal (TPAISCK) provides

timing for system Add side path alarm indication signal (PAIS)

assertion.

TPAISCK is a clock of arbitrary phase and frequency within the limits

specified in the A.C. Timing section of this document.

Inputs TPAIS and TPAISFP are sampled on the rising edge of

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