PM5316 datasheet(71/491 Pages) PMC

71 / 491 page

SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

• The accepted page.

• The expected page.

Section trace identifier data bytes from the receive stream are written into the capture page. The

expected identifier message is downloaded by the microprocessor into the expected page. On

receipt of a trace identifier byte, it is written into the next location in the capture page. The

received byte is compared with the data from the previous message in the capture page. The

identifier message is accepted if it is received unchanged three times, or optionally, five times.

The accepted message is then compared with the expected message.

If enabled, an interrupt is generated if the accepted message changes from “matching” the

expected message to “mismatching” and vice versa. If the current message differs from the

previous message for eight consecutive messages, the received message is declared unstable. The

received message is declared stable once the received message passes the persistency criterion

(three or five identical receptions) for being accepted. Note: An interrupt may be optionally

generated on entry to and exit from the unstable state. Optionally, line AIS may be inserted in the

received stream when the receive message is in the mismatched or unstable state.

The length of the section trace identifier message is selectable between 16-bytes and 64-bytes.

When programmed for 16-byte messages, the section trace buffer synchronizes to the byte with

the most significant bit set to high and places the byte at the first location in the capture page.

When programmed for 64-byte messages, the section trace buffer synchronizes to the trailing

carriage return (CR = 0DH), line feed (LF = 0AH) sequence and places the next byte at the head

of the capture page. This enables the section trace message to be appropriately aligned for

interpretation by the microprocessor. Synchronization may be disabled. In this case, the memory

acts as a circular buffer.

Mode 2 section trace identifier operation is also supported. For mode 2 support, a stable message

is declared when forty-eight of the same section trace identifier message (J0) bytes are received.

Once in the stable state, an unstable state is declared when one or more errors are detected in

three consecutive 16-byte windows.

10.4

Receive Line Overhead Processor (RLOP)

The Receive Line Overhead Processor block (RLOP) processes the line overhead (multiplexer

section) of the receive STS-3 (STM-1) stream. The block delares the LAIS and LRDI alarms. In

Addition the RLOP detects and accumulates B2 errors, accumulated L-REI and extracts the

K1/K2 APS bytes. The extracted automatic protection switch bytes (K1, K2) are supplied to the

RASE block for further processing and alarm declaration.

An interrupt output is provided that may be activated by declaration or removal of line AIS, line

RDI, protection switching byte failure alarm, a change of APS code value, a single B2 error

event, or a single line REI event. Each interrupt source is individually maskable.

PM5316 Datasheet(PDF) 71 Page - PMC-Sierra, Inc