PM5316 datasheet(60/491 Pages) PMC

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

Pin Name

Pin Type

No.

Function

APL[3] set high to mark the path trace byte (J1). Optionally, the

AC1J1V1[3] signal pulses high on the V1 byte to indicate tributary

multiframe boundaries.

Optional marking of the J1 and V1 bytes is controlled using the

DISJ1V1 bit in the TPPS Path Configuration register. Setting

DISJ1V1 bit high enables pointer interpretation on the Add bus.

Valid H1 and H2 pointer bytes must be provided on the Add data

bus signals (AD[23:16]) to allow the J1 position to be identified.

Optionally, the H4 byte could be provided on the Add data bus

signals (AD[23:16]) to allow the V1 position to be identified.

When using the Add bus TSI functionality, the AD[7:0], AD[15:8],

AD[23:16] and AD[31:24] Add buses must be frame aligned to have

the C1 pulses of the associated AC1J1V1 signals high

simultaneously.

AC1J1V1[3] is sampled on the rising edge of ACK.

AFP[3]

U30

The active high Add bus reference frame position signal #3 (AFP[3])

is defined when the AFPEN bit in the Add Bus Configuration register

is set high. AFP[3] indicates when the first byte of the synchronous

payload envelope (SPE byte 1 of STS-1 #1) of the SONET/SDH

stream is available on the AD[31:24] bus. Note that AFP[3] has a

fixed relationship to the SONET/SDH frame; the start of the SPE is

determined by the STS (AU) pointer and may change relative to

AFP[3]. The DISJ1V1 bit in the SPECTRA-4x155 TPPS Path

Configuration register must be set high in this mode to enable

pointer interpretation on the Add bus. Valid H1 and H2 pointer bytes

must be provided on the Add data bus (AD[23:16]) to allow the J1

position to be identified. Optionally, the H4 byte could be provided

on the Add data bus to allow the V1 position to be identified.

When using the Add bus TSI functionality, the AD[7:0], AD[15:8],

AD[23:16] and AD[31:24] Add buses must be frame aligned to have

the C1 pulses of the associated AC1J1V1 signals high

simultaneously.

AFP[3] is sampled on the rising edge of ACK.

AC1J1V1[4]/

Input

AB30

The Add bus composite timing signal #4 (AC1J1V1[4]) is defined

when the AFPEN bit in the Add Bus Configuration is set low.

AC1J1V1[4] identifies the frame and optionally the payload and

tributary multiframe boundaries on the Add data bus signals

AD[31:24]. AC1J1V1[4] pulses high with the Add bus payload active

signal #4 (APL[1]) set low to mark the first STS-1 (STM-0/AU-3)

Identification byte (C1). Optionally, the AC1J1V1[4] pulses high with

APL[4] set high to mark the path trace byte (J1). Optionally, the

AC1J1V1[4] signal pulses high on the V1 byte to indicate tributary

multiframe boundaries.

Optional marking of the J1 and V1 bytes is controlled using the

DISJ1V1 bit in the TPPS Path Configuration register. Setting

DISJ1V1 bit high enables pointer interpretation on the Add bus.

Valid H1 and H2 pointer bytes must be provided on the Add data

bus signals (AD[31:24]) to allow the J1 position to be identified.

Optionally, the H4 byte could be provided on the Add data bus

signals (AD[31:24]) to allow the V1 position to be identified.

PM5316 Datasheet(PDF) 60 Page - PMC-Sierra, Inc

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