PM5316 datasheet(67/491 Pages) PMC

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

Functional Description

10.1

Receive Line Interface and CRSI

The Receive Line Interface and the Clock Recover/Serial-to-Parallel Convertor (CRSI) blocks

perform PECL conversion, clock and data recovery on the incoming 155.52 Mbit/s data stream,

and serial-to-parallel conversion based on the recovered SONET/SDH A1/A2 framing pattern.

The blocks allow the SPECTRA-4x155 to directly interface with optical modules (ODLs) or

other medium interfaces.

10.1.1 Clock Recovery Unit (CRU)

The clock recovery unit (CRU) inside the CRSI block recovers a clock from the incoming bit

serial data stream. The CRU is fully compliant with SONET/SDH jitter tolerance requirements. It

uses a low frequency 19.44 MHz reference clock to train and monitor its clock recovery phase-

locked loop (PLL). Under LOS conditions, the CRU will continue to output a line rate clock that

is locked to this reference for keep-alive purposes. As part of its feature set, the CRU provides

status bits that indicate whether it is locked to data or to the reference clock. The unit also

supports diagnostic loopback and a LOS input that squelches normal input data.

Initially, the PLL locks to the reference clock, REFCLK. Once the frequency of the recovered

clock is within 488 ppm of the reference clock, the PLL attempts to lock to the data. Once in data

lock, the PLL will revert to the reference clock if no data transitions occur in 80 bit periods or if

the recovered clock drifts beyond approximately 488 ppm of the reference clock.

When the transmit clock is derived from the recovered clock (loop timing), the accuracy of the

transmit clock is directly related to the REFCLK reference accuracy under LOS conditions. In

applications that are required to meet the Telcordia GR-253-CORE SONET Network Element

free-run accuracy specification, the reference must be within +/-20 ppm. When not loop timed,

the REFCLK accuracy may be relaxed to +/-50 ppm.

The loop filter transfer function is optimized to enable the PLL to track the jitter, yet tolerate the

minimum transition density expected in a received SONET/SDH data signal. The total loop

dynamics of the clock recovery PLL yield a jitter tolerance that exceeds the minimum tolerance

proposed for SONET equipment by GR-253-CORE as shown in Figure 5.

PM5316 Datasheet(PDF) 67 Page - PMC-Sierra, Inc