PM5316 datasheet(91/491 Pages) PMC

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

The operation of the APGM block is identical to that of the DPGM block of RPPS. Refer to

section 10.9.4.

10.10.2 Transmit Pointer Interpreter Processor (TPIP)

The Transmit Pointer Interpreter Processor (TPIP) block of TPPS takes STS-1 (STM-0/AU-3)

SPE (VC-3) or equivalent data stream from the Add bus, interprets the pointer (H1, H2), indicates

the J1 byte location and detects alarm conditions (for example, PAIS).The indicated J1 byte

position will be used only when the APFEN bit in the Add Bus Configuration register is set high

or the DISJ1V1 bit is set high in the TPPS Path Configuration register of a specific TPPS. When

supplying a valid telecom Add interface with valid J1 pulse, the TPIP pointer alarms may still be

used.

Pointer Interpreter

The TPIP block allows the SPECTRA-4x155 to operate with TelecomBus-like back plane

systems that do not indicate the J1 byte position. The TPIP block can be enabled using the

DISJ1V1 bit in the SPECTRA-4x155 Path Configuration register. When enabled, the TPIP takes

a STS-1 (STM-0/AU-3) SONET/SDH stream from the System Side Interface block, processes the

stream, identifies the J1 byte location and provides the stream to the corresponding Transmit

TelecomBus Aligner block. The block will interpret the Add Bus pointer to determine the J1 byte

location. Refer to section 10.9.1 for details of the interpreter state machine.

The same pointer interpreter will be used to determine the J1 byte location when the APFEN

control bit is set high. In this mode the Add bus will only a frame pulse identifying the 1st SPE

byte of the Add bus.

When supplying a valid J1 pulse which is to be used from the Add Bus (DISJ1V1 and AFP set

low), the pointer interpreter will still run and all declared alarms are still valid provided there are

valid H1, H2 pointers on the Add bus. These alarms can also be used to force consequential

actions.

Slave TPIP blocks are also able to verify for a valid concatenation indicator in the H1 and H2

bytes.

The LOP, LOPCON or PAISCON alarms declared by the pointer interpreter block can be used to

force transmit path AIS.

Error Monitoring

Three 16-bit counters are provided to accumulate path BIP-8 errors (B3) and path REI. The

contents of the counters may be transferred to holding registers, and the counters reset under

microprocessor control. Refer to section 10.9.1 for details on error monitoring.

PM5316 Datasheet(PDF) 91 Page - PMC-Sierra, Inc