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PM5316 Datasheet(PDF) 2 Page - PMC-Sierra, Inc

Part # PM5316
Description  SONET/SDH Payload Extractor/Aligner(4 x 155 Mbit/s)
PDF  491 Pages
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Manufacturer  PMC [PMC-Sierra, Inc]
Direct Link  http://www.pmc-sierra.com
Logo PMC - PMC-Sierra, Inc

PM5316 Datasheet(HTML) 2 Page - PMC-Sierra, Inc

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)
Production
Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use
2
Document ID: PMC-1990822, Issue 4
Issue
No.
Issue
Date
Details of Change
Issue 4
Mar
2001
De-documented all Transport Path Overhead port (TPOH) functionality
Added Overhead byte processing information in operation section.
Issue 3
Jan
2001
•
Removed TIU2E and TIU2I registers bits from registers 1n2Dh and 1n31h
respectively.
•
DOPJ[1:0] register bit in the TTAL block (register 1nD1h) have been removed.
•
DOPJ[1:0] register bit in the RTAL block (register 1n59h) have been redefined.
•
PRBS monitoring mode needs two bits to be programmed. Mode setting in
both the DPGM (register 1n7Ah) and APGM (register 1nFAh) is now defined via
two mode bits MON_GMODE[1:0].
•
RSOP Section B1 error counters (0m16h and Om17h registers) may also be
transferred upon a write to either register.
•
Master test register bit 3 to 7 are defined as R/W instead of just W.
•
Pin out diagram has changed format to improve readibility but the pinout
remains the SAME.
•
Due to clear on write auxiliary interrupts, tZint timing is specified for
microprocessor writes to clear device interrupt pin.
•
Analog supplies AVD/AVS are specified at 5% instead of 10%.
•
Consistent naming or STM1-CONCAT to STM1_CONCAT (underscore) register
bit in registers 1n00h and 1n80h.
•
Power supply board recommendations have been changed in section 13.8.
Separate supplies are no longer recommended.
•
Specific PECL input currents are given in section 17, D.C. Characteristics.
•
RAD does not contain transmitted K1/K2 bytes under generation of AIS-L on
the transmit stream.
•
TAD port is limited to accumulating a maximum of 15 REI
Issue 2
Sept
2000
•
Additional feature explanations/ clarifications
•
Timing Change on drop interface in 19.44 Mhz mode
•
Addition of register bits CONCAT, TPOH_DIS, ATSI_FORCE and ATSI_RESET
•
Definition changes of LOPCONRALM and PAISCONRALM.
•
Added Section describing loopbacks
•
DC Characteristics up to date and complete
•
Added RTC_EN register bit.
Issue 1
June
2000
Preliminary release of datasheet



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