PM5316 datasheet(72/491 Pages) PMC

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

10.4.1 Line RDI Detect

The Line RDI Detect Block within the RLOP detects the presence of remote defect indication

(LRDI) in the receive stream. Line RDI is declared when a 110 binary pattern is detected in bits

6, 7, and 8 of the K2 byte, for three or five consecutive frames. Line RDI is removed when any

pattern other than 110 is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive

frames. The LRDI signal is optionally reported on the SALM output pin when enabled by the

LRDISALM Section Alarm Output Control #2 Register bit.

10.4.2 Line AIS Detect

The Line AIS Block detects the presence of an alarm indication signal (LAIS) in the receive

stream. Line AIS is declared when a 111 binary pattern is detected in bits 6, 7, and 8 of the K2

byte, for three or five consecutive frames. Line AIS is removed when any pattern other than 111

is detected in bits 6, 7, and 8 of the K2 byte for three or five consecutive frames. The LRDI signal

is optionally reported on the SALM output pin when enabled by the LAISSALM Section Alarm

Output Control #1 Register bit.

10.4.3 Error Monitor Block

The Error Monitor Block calculates the received line BIP-8 error detection codes based on the

Line Overhead bytes and SPEs of the STS-3 (STM-1) stream. The line BIP-8 code is a bit

interleaved parity calculation using even parity. Details are provided in the references. The

calculated BIP-8 codes are compared with the BIP-8 codes extracted from the following frame.

Any differences indicate that a line layer bit error has occurred. As well, the RLOP can be

configured to count a maximum of only one BIP error per frame. Accumulated B2 errors are

passed to the RASE block for processing and the declaration of signal degrade and signal failure.

This block also extracts the line REI code from the M1 byte. The REI code is contained in bits 2

to 8 of the M1 byte, and represents the number of line BIP-8 errors that were detected in the last

frame by the far end. The REI code value has 25 legal values (0 to 24) for an STS-3 (STM-1)

stream. Illegal values are interpreted as zero errors.

The Error Monitor Block accumulates B2 error events and REI events in two 20-bit saturating

counters that can be read via the microprocessor interface. The contents of these counters may be

transferred to internal holding registers by writing to any one of the counter addresses, or by

using the TIP register bit feature. During a transfer, the counter value is latched and the counter is

reset to zero (or one, if there is an outstanding event). Note: these counters should be polled at

least once per second to avoid saturation.

The B2 error event and REI event counters can be optionally configured to accumulate only

“word” errors. A B2 word error is defined as the occurrence of one or more B2 bit error events

during a frame. In STS-3 (STM-1) framing, a REI word event is defined as the occurrence of one

or more REI bit events during a frame. The B2 error or REI event counter is incremented by one

for each frame in which a B2 word error or REI event occurs.

PM5316 Datasheet(PDF) 72 Page - PMC-Sierra, Inc