PM5316 datasheet(61/491 Pages) PMC

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SONET/SDH Payload Extractor/Aligner (SPECTRA-4x155)

Production

Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use

Document ID: PMC-1990822, Issue 4

Pin Name

Pin Type

No.

Function

When using the Add bus TSI functionality, the AD[7:0], AD[15:8],

AD[23:16] and AD[31:24] Add buses must be frame aligned to have

the C1 pulses of the associated AC1J1V1 signals high

simultaneously.

AC1J1V1[4] is sampled on the rising edge of ACK.

AFP[4]

AB30

The active high Add bus reference frame position signal #4 (AFP[4])

is defined when the AFPEN bit in the Add Bus Configuration is set

high. AFP[4] indicates when the first byte of the synchronous

payload envelope (SPE byte 1 of STS-1 #1) of the SONET/SDH

stream is available on the AD[31:24] bus. Note that AFP[4] has a

fixed relationship to the SONET/SDH frame; the start of the SPE is

determined by the STS (AU) pointer and may change relative to

AFP[4]. The DISJ1V1 bit in the TPPS Path Configuration register

must be set high in this mode to enable pointer interpretation on the

Add bus. Valid H1 and H2 pointer bytes must be provided on the

Add data bus (AD[31:24]) to allow the J1 position to be identified.

Optionally, the H4 byte could be provided on the Add data bus to

allow the V1 position to be identified.

When using the Add bus TSI functionality, the AD[7:0], AD[15:8],

AD[23:16] and AD[31:24] Add buses must be frame aligned to have

the C1 pulses of the associated AC1J1V1 signals high

simultaneously.

AFP[4] is sampled on the rising edge of ACK.

ADP[1]

Input

G28

The Add bus data parity signal #1 (ADP[1]) indicates the parity of

the Add bus #1 signals. The Add data bus (AD[7:0]) is always

included in parity calculations. Register bits in the Add Bus

Configuration register control the inclusion of the APL[1] and

AC1J1V1[1]/AFP[1] signals in parity calculations and the sense

(odd/even) of the parity.

ADP[1] is sampled on the rising edge of ACK.

ADP[2]

Input

M28

The Add bus data parity signal #2 (ADP[2]) indicates the parity of

the Add bus #2 signals. The Add data bus (AD[15:8]) is always

included in parity calculations. Register bits in the Add Bus

Configuration register control the inclusion of the APL[2] and

AC1J1V1[2]/AFP[2] signals in parity calculations and the sense

(odd/even) of the parity.

ADP[2] is sampled on the rising edge of ACK.

ADP[3]

Input

W31

The Add bus data parity signal #3 (ADP[3]) indicates the parity of

the Add bus #3 signals. The Add data bus (AD[23:16]) is always

included in parity calculations. Register bits in the Add Bus

Configuration register control the inclusion of the APL[3] and

AC1J1V1[3]/AFP[3] signals in parity calculations and the sense

(odd/even) of the parity.

ADP[3] is sampled on the rising edge of ACK.

ADP[4]

Input

AD30

The Add bus data parity signal #4 (ADP[4]) indicates the parity of

the Add bus #4 signals. The Add data bus (AD[31:24]) is always

included in parity calculations. Register bits in the Add Bus

Configuration register control the inclusion of the APL[4] and

AC1J1V1[4]/AFP[4] signals in parity calculations and the sense

PM5316 Datasheet(PDF) 61 Page - PMC-Sierra, Inc

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