PM5357 datasheet(89/432 Pages) PMC

89 / 432 page

PRODUCTION

S/UNI-622-POS

PMC-Sierra, Inc.

PM5357

S/UNI-622-POS

DATASHEET

PMC-1980911

ISSUE 5

SATURN USER NETWORK INTERFACE (622-POS)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

Framing and Identity Insert

The Framing and Identity Insert Block inserts the framing bytes (A1, A2) and

trace/growth bytes (J0/Z0) into the STS-12c/STM-4-4c frame. Framing bit errors

may be continuously inserted under register control for diagnostic purposes.

Scrambler

The Scrambler Block utilizes a frame synchronous scrambler to process the

transmit stream when enabled through an internal register accessed via the

microprocessor interface. The generating polynomial is x7 + x6 + 1. Precise

details of the scrambling operation are provided in the references. Note that the

framing bytes and the identity bytes are not scrambled. All zeros may be

continuously inserted (after scrambling) under register control for diagnostic

purposes.

The POUT[7:0] outputs are provided by the Scrambler block and are updated

with timing aligned to TCLK. It also provides the FPOUT signal.

10.10 Transmit Line Overhead Processor (TLOP)

The Transmit Line Overhead Processor (TLOP) provides line level alarm signal

insertion, and line BIP-96 insertion (B2). In addition, it inserts the line data

communication provided serially on input TLD.

APS Insert

The APS Insert Block inserts the two automatic protection switch (APS) channel

bytes in the Line Overhead (K1 and K2) into the transmit stream when enabled

by an internal register.

Data Link Insert

The Data Link Insert Block inserts the line data communication channel (DCC)

(bytes D4 to D12) into the STS-12c/STM-4-4c stream when enabled by an

internal register. The D4 to D12 bytes are input serially using the TLD signal at a

nominal 576 kbit/s rate. Timing for processing of the line DCC is provided by the

TLDCLK output. TLDCLK is derived from a 2.16 MHz clock that is gapped to

yield an average frequency of 576 kHz.

Line BIP Calculate

The Line BIP Calculate Block calculates the line BIP-96 error detection code (B2)

based on the line overhead and synchronous payload envelope of the transmit

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