PM5357 datasheet(12/432 Pages) PMC

12 / 432 page

PRODUCTION

S/UNI-622-POS

PMC-Sierra, Inc.

PM5357

S/UNI-622-POS

DATASHEET

PMC-1980911

ISSUE 5

SATURN USER NETWORK INTERFACE (622-POS)

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS’ INTERNAL USE

LIST OF TABLES

TABLE 1: POINTER INTERPRETER EVENT (INDICATIONS) DESCRIPTION......................................... 71

TABLE 2: POINTER INTERPRETER TRANSITION DESCRIPTION ......................................................... 73

TABLE 3: HDLC BYTE SEQUENCES........................................................................................................ 80

TABLE 4: HDLC BYTE SEQUENCES........................................................................................................ 90

TABLE 5: OBR MISMATCH MECHANISM................................................................................................. 92

TABLE 6: REGISTER MEMORY MAP ..................................................................................................... 101

TABLE 7: RECEIVE INITIATION LEVEL VALUES ................................................................................... 275

TABLE 8: TRANSMIT INITIATION LEVEL VALUES................................................................................. 294

TABLE 9: INTER PACKET GAPING VALUES.......................................................................................... 295

TABLE 10: TEST MODE REGISTER MEMORY MAP ............................................................................. 336

TABLE 11: INSTRUCTION REGISTER (LENGTH - 3 BITS).................................................................... 339

TABLE 12: S/UNI-622-POS IDENTIFICATION REGISTER ..................................................................... 339

TABLE 13: S/UNI-622-POS BOUNDARY SCAN REGISTER .................................................................. 339

TABLE 14: SETTINGS FOR SONET OR SDH OPERATION................................................................... 357

TABLE 15: RECOMMENDED BERM SETTINGS .................................................................................... 359

TABLE 16: PATH RDI AND EXTENDED RDI REGISTER SETTINGS ..................................................... 359

TABLE 17: 1+1 APS REGISTER 0X06 SETTINGS.................................................................................. 367

TABLE 18: ABSOLUTE MAXIMUM RATINGS ......................................................................................... 392

TABLE 19: D.C CHARACTERISTICS ...................................................................................................... 393

TABLE 20: MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 51) ....................................... 396

TABLE 21: MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 52) ..................................... 398

TABLE 22: RSTB TIMING (FIGURE 53) .................................................................................................. 400

TABLE 23: TRANSMIT PARALLEL LINE INTERFACE TIMING (FIGURE 54) ......................................... 401

TABLE 24: RECEIVE PARALLEL LINE INTERFACE TIMING (FIGURE 55) ........................................... 402

TABLE 25: RECEIVE SERIAL LINE INTERFACE TIMING (FIGURE 56)................................................. 403

TABLE 26: TRANSMIT UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 57) ........................ 404

TABLE 27: RECEIVE UTOPIA LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 58) .......................... 406

TABLE 28: TRANSMIT UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 59) ........................ 408

TABLE 29: RECEIVE UTOPIA LEVEL 3 SYSTEM INTERFACE TIMING (FIGURE 60) .......................... 410

TABLE 30: TRANSMIT POS-PHY LEVEL 2 SYSTEM INTERFACE TIMING (FIGURE 61) ......................411

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