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AM69 Datasheet(PDF) 138 Page - Texas Instruments |
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AM69 Datasheet(HTML) 138 Page - Texas Instruments |
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138 / 312 page  Table 5-121. Connectivity Requirements ALY BALL NUMBER AND BALL NUMBER BALL NAME CONNECTION REQUIREMENT P38 B23 OSC1_XI Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low-level, if unused. T38 A24 WKUP_OSC0_XI G37 F17 TRSTN U1 R1 DDR0_DQS0P AA1 V1 DDR0_DQS1P AF1 AD1 DDR0_DQS2P AJ1 AG1 DDR0_DQS3P A16 B1 DDR1_DQS0P A13 E1 DDR1_DQS1P A8 L1 DDR1_DQS2P A3 P1 DDR1_DQS3P T1 – DDR2_DQS0P N1 – DDR2_DQS1P H1 – DDR2_DQS2P E1 – DDR2_DQS3P A18 – DDR3_DQS0P A21 – DDR3_DQS1P A26 – DDR3_DQS2P A29 – DDR3_DQS3P AC8 AC7 DDR0_RET G8 G8 DDR1_RET L8 - DDR2_RET G27 - DDR3_RET K28 G26 VMON1_ER_VSYS N27 L25 VMON2_IR_VCPU J30 K30 VMON3_IR_VEXT1P8 P28 M26 VMON4_IR_VEXT1P8 R29 M29 VMON5_IR_VEXT3P3 P36 E26 MCU_ADC0_AIN0 Each of these balls can be connected to VSS through a separate external pull resistor or can be connected directly to VSS to ensure these balls are held to a valid logic low-level, if unused. V36 F25 MCU_ADC0_AIN1 T34 F23 MCU_ADC0_AIN2 T36 A28 MCU_ADC0_AIN3 P34 E24 MCU_ADC0_AIN4 R37 D27 MCU_ADC0_AIN5 R33 A26 MCU_ADC0_AIN6 V38 B27 MCU_ADC0_AIN7 Y38 C32 MCU_ADC1_AIN0 Y34 B33 MCU_ADC1_AIN1 V34 B31 MCU_ADC1_AIN2 W37 B29 MCU_ADC1_AIN3 AA37 D31 MCU_ADC1_AIN4 W33 A32 MCU_ADC1_AIN5 U33 A30 MCU_ADC1_AIN6 Y36 C28 MCU_ADC1_AIN7 AM69A, AM69 SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024 www.ti.com 138 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: AM69A AM69 |
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