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AM69 Datasheet(PDF) 248 Page - Texas Instruments

Part # AM69
Description  AM69x Processors, Silicon Revision 1.0
PDF  312 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
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AM69 Datasheet(HTML) 248 Page - Texas Instruments

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6.10.5.17.1.1 Legacy SDR Mode
Table 6-59, Figure 6-77, Table 6-60, and Figure 6-78 present timing requirements and switching characteristics
for MMC0 – Legacy SDR Mode.
Table 6-59. MMC0 Timing Requirements – Legacy SDR Mode
see Figure 6-77
NO.
MIN
MAX
UNIT
LSDR1
tsu(cmdV-clkH)
Setup time, MMC0_CMD valid before MMC0_CLK rising edge
2.5
ns
LSDR2
th(clkH-cmdV)
Hold time, MMC0_CMD valid after MMC0_CLK rising edge
6.5
ns
LSDR3
tsu(dV-clkH)
Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
2.5
ns
LSDR4
th(clkH-dV)
Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
6.5
ns
Figure 6-77. MMC0 – Legacy SDR – Receive Mode
Table 6-60. MMC0 Switching Characteristics – Legacy SDR Mode
see Figure 6-78
NO.
PARAMETER
MIN
MAX
UNIT
fop(clk)
Operating frequency, MMC0_CLK
25
MHz
LSDR5
tc(clk)
Cycle time, MMC0_CLK
40
ns
LSDR6
tw(clkH)
Pulse duration, MMC0_CLK high
18.7
ns
LSDR7
tw(clkL)
Pulse duration, MMC0_CLK low
18.7
ns
LSDR8
td(clkL-cmdV)
Delay time, MMC0_CLK falling edge to MMC0_CMD transition
–3.2
3.8
ns
LSDR9
td(clkL-dV)
Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
–3.2
3.8
ns
Figure 6-78. MMC0 – Legacy SDR – Transmit Mode
AM69A, AM69
SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024
www.ti.com
248
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Product Folder Links: AM69A AM69



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